GTY and GTYP Transceiver User Clock Switching Characteristics

Versal Premium Series Data Sheet: DC and AC Switching Characteristics (DS959)
Document ID
DS959
Release Date
2024-06-25
Revision
1.7 English
Table 1. GTY Transceiver User Clock Switching Characteristics
Symbol Description 1 Data Width Conditions (Bit) Performance as a Function of Speed Grade and Operating Voltage (VCCINT) Units
0.88V (H) 0.80V (M) 0.725V (L) 0.70V (L)
Internal Logic Interconnect Logic -2 -2 -1 -2LLI -2 -1
FTXOUTPMA TXOUTCLK maximum frequency sourced from OUTCLKPMA 664.063 664.063 664.063 664.063 664.063 644.531 MHz
FRXOUTPMA RXOUTCLK maximum frequency sourced from OUTCLKPMA 664.063 664.063 664.063 664.063 664.063 644.531 MHz
FTXOUTPROGDIV TXOUTCLK maximum frequency sourced from OUTPROGDIV 1024.000 1024.000 664.063 664.063 664.063 644.531 MHz
FRXOUTPROGDIV RXOUTCLK maximum frequency sourced from OUTPROGDIV 1024.000 1024.000 664.063 664.063 664.063 644.531 MHz
FTXIN TXUSRCLK maximum frequency 16 16 440.781 440.781 415.040 402.832 402.832 402.832 MHz
32 220.391 220.391 207.520 201.416 201.416 201.416 MHz
32 32 440.781 440.781 415.040 402.832 402.832 402.832 MHz
64 220.391 220.391 207.520 201.416 201.416 201.416 MHz
64 64 440.781 440.781 415.039 402.832 402.832 402.832 MHz
128 220.391 220.391 207.520 201.416 201.416 201.416 MHz
20 20 352.625 352.625 332.032 352.625 352.625 322.266 MHz
40 176.313 176.313 166.016 176.313 176.313 161.133 MHz
40 40 664.063 664.063 664.063 664.063 664.063 644.531 MHz
80 176.313 176.313 166.016 176.313 176.313 161.133 MHz
80 80 352.625 352.625 332.032 352.625 352.625 322.266 MHz
160 176.313 176.313 166.016 176.313 176.313 161.133 MHz
FRXIN RXUSRCLK maximum frequency 16 16 440.781 440.781 415.040 402.832 402.832 402.832 MHz
32 220.391 220.391 207.520 201.416 201.416 201.416 MHz
32 32 440.781 440.781 415.040 402.832 402.832 402.832 MHz
64 220.391 220.391 207.520 201.416 201.416 201.416 MHz
64 64 440.781 440.781 415.039 402.832 402.832 402.832 MHz
128 220.391 220.391 207.520 201.416 201.416 201.416 MHz
20 20 352.625 352.625 332.032 352.625 352.625 322.266 MHz
40 176.313 176.313 166.016 176.313 176.313 161.133 MHz
40 40 664.063 664.063 664.063 664.063 664.063 644.531 MHz
80 176.313 176.313 166.016 176.313 176.313 161.133 MHz
80 80 352.625 352.625 332.031 352.625 352.625 322.266 MHz
160 176.313 176.313 166.016 176.313 176.313 161.133 MHz
  1. Clocking must be implemented as described in the Versal Adaptive SoC GTY and GTYP Transceivers Architecture Manual (AM002).
Table 2. GTYP Transceiver User Clock Switching Characteristics
Symbol Description 1 Data Width Conditions (Bit) Performance as a Function of Speed Grade and Operating Voltage (VCCINT) Units
0.88V (H) 0.80V (M) 0.725V (L) 0.70V (L)
Internal Logic Interconnect Logic -3 -2 -1 -2LLI -2 -1
FTXOUTPMA TXOUTCLK maximum frequency sourced from OUTCLKPMA 664.063 664.063 664.063 664.063 664.063 644.531 MHz
FRXOUTPMA RXOUTCLK maximum frequency sourced from OUTCLKPMA 664.063 664.063 664.063 664.063 664.063 644.531 MHz
FTXOUTPROGDIV TXOUTCLK maximum frequency sourced from OUTPROGDIV 1024.000 1024.000 1000 664.063 664.063 644.531 MHz
FRXOUTPROGDIV RXOUTCLK maximum frequency sourced from OUTPROGDIV 1024.000 1024.000 1000 664.063 664.063 644.531 MHz
FTXIN TXUSRCLK maximum frequency 16 16 511.719 440.781 415.039 402.832 402.832 402.832 MHz
32 255.859 220.391 207.520 201.416 201.416 201.416 MHz
32 32 511.719 440.781 415.039 402.832 402.832 402.832 MHz
64 255.859 220.391 207.520 201.416 201.416 201.416 MHz
64 64 511.719 (LPM) 500 415.039 500 500 402.832 MHz
500 (DFE)
128 255.859 (LPM) 250 207.520 250 250 201.416 MHz
250 (DFE)
20 20 409.375 352.625 332.032 352.625 352.625 322.266 MHz
40 204.688 176.313 166.016 176.313 176.313 161.133 MHz
40 40 664.063 664.063 664.063 664.063 664.063 644.531 MHz
80 204.688 176.313 166.016 176.313 176.313 161.133 MHz
80 80 409.375 (LPM) 400 332.031 400 400 322.266 MHz
400 (DFE)
160 204.688 (LPM) 200 166.016 200 200 161.133 MHz
200 (DFE)
FRXIN RXUSRCLK maximum frequency 16 16 511.719 440.781 415.039 402.832 402.832 402.832 MHz
32 255.859 220.391 207.520 201.416 201.416 201.416 MHz
32 32 511.719 440.781 415.039 402.832 402.832 402.832 MHz
64 255.859 220.391 207.520 201.416 201.416 201.416 MHz
64 64 511.719 (LPM) 500 415.039 500 500 402.832 MHz
500 (DFE)
128 255.859 (LPM) 250 207.520 250 250 201.416 MHz
250 (DFE)
20 20 409.375 352.625 332.032 352.625 352.625 322.266 MHz
40 204.688 176.313 166.016 176.313 176.313 161.133 MHz
40 40 664.063 664.063 664.063 664.063 664.063 644.531 MHz
80 204.688 176.313 166.016 176.313 176.313 161.133 MHz
80 80 409.375 (LPM) 400 332.031 400 400 322.266 MHz
400 (DFE)
160 204.688 (LPM) 200 166.016 200 200 161.133 MHz
200 (DFE)
  1. Clocking must be implemented as described in the Versal Adaptive SoC GTY and GTYP Transceivers Architecture Manual (AM002).