Programmable Logic Integrated Block for PCIe

Versal Premium Series Data Sheet: DC and AC Switching Characteristics (DS959)

Document ID

DS959

Release Date

2024-06-25

Revision

1.7 English

More information and documentation on solutions for PCI Express designs can be found at PCI Express . The Versal Architecture and Product Data Sheet: Overview (DS950) lists how many blocks are in each Versal device.

Table 1. Maximum Performance for Programmable Logic Integrated Block for PCIe Rev. 5.0
Symbol	Description^{1, 2, 3, 4}	Performance as a Function of Speed Grade and Operating Voltage (V_CCINT)							Units
		0.88V (H)		0.80V (M)		0.725V (L)	0.70V (L)
		-3	-2	-2	-1	-2LLI	-2	-1
F_PIPECLK	Pipe clock maximum frequency	500	500	500	500	500	500	500	MHz
F_CORECLK	Core clock maximum frequency	500	500	500	500	500	500	500	MHz
F_APBCLK	APB clock maximum frequency	250	250	250	250	250	250	250	MHz
This table only specifies the AC switching characteristics of the identified integrated block for PCIe. AMD LogiCORE™ IP solutions for PCIe that incorporate this block also integrate clocking, transceivers, logic, and block memory. LogiCORE IP solutions for PCIe must achieve timing closure during design implementation in the target device, including user-contributed application logic. For information and technical guidance on resource use and minimum device requirements, see the Versal Adaptive SoC Integrated Block for PCI Express LogiCORE IP Product Guide (PG343) and Versal Adaptive SoC DMA and Bridge Subsystem for PCI Express Product Guide (PG344). PCI Express Gen5 operation is supported for x1, x2, and x4 widths. PCI Express Gen5 operation is supported in -3H, -2H, and -2M speed grades. PCI Express Gen4 operation is supported for x1, x2, x4, and x8 widths.