DC Characteristics Over Recommended Operating Conditions

Versal Premium Series Data Sheet: DC and AC Switching Characteristics (DS959)

Document ID
DS959
Release Date
2024-06-25
Revision
1.7 English
Table 1. DC Characteristics Over Recommended Operating Conditions
Symbol Description Min Typ 1 Max Units
CIN 2 , 3 HDIO and PSIO die input capacitance at the pad 3.50 pF
XPIO die input capacitance at the pad 1.75 pF
IL 3

For XC devices, HDIO, XPIO, and PSIO input or output leakage current per pin (sample-tested)

15 µA

For XQ devices, HDIO, XPIO, and PSIO input or output leakage current per pin (sample-tested)

20 µA
IRPU 3 Pad pull-up (when selected) at VIN = 0V, VCCO = 3.3V 60 200 µA
Pad pull-up (when selected) at VIN = 0V, VCCO = 2.5V 50 169 µA
Pad pull-up (when selected) at VIN = 0V, VCCO = 1.8V 29 120 µA
Pad pull-up (when selected) at VIN = 0V, VCCO = 1.5V 30 120 µA
Pad pull-up (when selected) at VIN = 0V, VCCO = 1.2V 10 100 µA
IRPD Pad pull-down (when selected) at VIN = 3.3V 60 200 µA
Pad pull-down (when selected) at VIN = 1.8V 29 120 µA
ICC_FUSE VCC_FUSE supply current during eFUSE programming 165 mA
Battery Supply Current for VP1002, VP1052, VP1102, VP1202, and VP1402 Devices
ICC_BATT 4, 5 Battery supply current at VCC_BATT = 1.20V, RTC disabled 160 nA
Battery supply current at VCC_BATT = 1.50V, RTC disabled 320 nA
Battery supply current at VCC_BATT = 1.20V, RTC enabled 1360 nA
Battery supply current at VCC_BATT = 1.50V, RTC enabled 1930 nA
Battery Supply Current for VP1502, VP1552, and VP2502 Devices
ICC_BATT 4, 5 Battery supply current at VCC_BATT = 1.20V, RTC disabled 320 nA
Battery supply current at VCC_BATT = 1.50V, RTC disabled 640 nA
Battery supply current at VCC_BATT = 1.20V, RTC enabled 1520 nA
Battery supply current at VCC_BATT = 1.50V, RTC enabled 2250 nA
Battery Supply Current for VP1702 Devices
ICC_BATT 4, 5 Battery supply current at VCC_BATT = 1.20V, RTC disabled 480 nA
Battery supply current at VCC_BATT = 1.50V, RTC disabled 960 nA
Battery supply current at VCC_BATT = 1.20V, RTC enabled 1680 nA
Battery supply current at VCC_BATT = 1.50V, RTC enabled 2570 nA
Battery Supply Current for VP1802, VP1902, and VP2802 Devices
ICC_BATT 4, 5 Battery supply current at VCC_BATT = 1.20V, RTC disabled 640 nA
Battery supply current at VCC_BATT = 1.50V, RTC disabled 1280 nA
Battery supply current at VCC_BATT = 1.20V, RTC enabled 1840 nA
Battery supply current at VCC_BATT = 1.50V, RTC enabled 2890 nA
Calibrated programmable on-die termination (DCI) in XPIO banks 6 (measured per JEDEC specification)
R 8 Thevenin equivalent resistance of programmable input termination where x = target impedance of 48, 60, 120, or 240 –20% 7 ODT = RTT_x +20% 7 Ω
Uncalibrated programmable on-die termination in HDIO banks (measured per JEDEC specification)
R 8 Thevenin equivalent resistance of programmable input termination to VCCO/2 where ODT = RTT_48 –50% 48 +50% Ω
Differential termination Programmable differential termination (TERM_100) for XPIO banks –35% 100 +35% Ω
  1. Typical values are specified at nominal voltage, 25°C.
  2. This measurement represents the die capacitance at the pad, not including the package.
  3. Certain pins in some devices with multiple SLRs are connected to multiple SLR die pads in the package. For the MODE[3:0], POR_B, and PUDC_B pins in VP1502, VP1552, and VP2502 devices, multiply the characteristics by 2; in the VP1702 device, multiply the characteristics by 3; and in VP1802, VP1902, and VP2802 devices, multiply the characteristic by 4. For the REF_CLK0 pin in the VP1702, VP1802, and VP2802 devices and for the REF_CLK1 pin in VP1802 and VP2802 devices, multiply the characteristic by 2. See the Versal Architecture and Product Data Sheet: Overview (DS950) for device SLR counts. The IRPU characteristic does not apply to POR_B.
  4. Maximum value specified for worst case process at 25°C.
  5. Battery-backed RAM (BBRAM) is always enabled and included in ICC_BATT .
  6. VR resistor tolerance is (240Ω ±1%).
  7. The tolerance limits are specified after calibration with stable voltage and temperature.
  8. On-die input termination resistance, for more information see the Versal Adaptive SoC SelectIO Resources Architecture Manual (AM010).