AI Engine Switching Characteristics

Versal Premium Series Data Sheet: DC and AC Switching Characteristics (DS959)
Document ID
DS959
Release Date
2024-06-25
Revision
1.7 English

The following tables provide performance characteristics for the AI Engines. The Versal Architecture and Product Data Sheet: Overview (DS950) lists the devices that include the AI Engine and the number of AI Engine array rows, columns, and PL interface tiles.

Table 1. AI Engine Switching Characteristics
Symbol Description Performance as a Function of Speed Grade and Operating Voltage (VCCINT) Units
0.88V (H) 0.80V (M) 0.725V (L) 0.70V (L)
-3 -2 -1 -2LLI -2 -1
FMAX AI Engine array clock maximum frequency 1300 1250 1150 1050 1050 1000 MHz
FMAX_AI_PL AI Engine array to programmable logic interface 650 625 575 525 525 500 MHz
Table 2. AI Engine – PL Interface Performance
Connection Type Device Total Bandwidth 2, 3 as a Function of Speed Grade and Operating Voltage (VCCINT) Units
0.88V (H) 0.80V (M) 0.725V (L) 0.70V (L)
-3 -2 -1 -2LLI -2 -1
PL to AI Engine array interface 1 VP2502 1955.2 1880.0 1729.6 N/A 1579.2 1504.0 GB/s
VP2802 1955.2 1880.0 1729.6 N/A 1579.2 1504.0 GB/s
AI Engine array interface to AI Engine array 4 VP2502 1508.0 1450.0 1334.0 N/A 1218.0 1160.0 GB/s
VP2802 1508.0 1450.0 1334.0 N/A 1218.0 1160.0 GB/s
AI Engine array to AI Engine array interface 4 VP2502 1019.2 980.0 901.6 N/A 823.2 784.0 GB/s
VP2802 1019.2 980.0 901.6 N/A 823.2 784.0 GB/s
AI Engine array interface to PL VP2502 1466.4 1410.0 1297.2 N/A 1184.4 1128.0 GB/s
VP2802 1466.4 1410.0 1297.2 N/A 1184.4 1128.0 GB/s
  1. Not all of the AI Engine interface tiles are connected to the PL.
  2. Assumes all PL AXI4-Stream interfaces run at maximum frequency.
  3. AI Engine array interface tiles have interfaces to both the PL and NoC. Routing to these interfaces share the same streaming interconnect resources inside the AI Engine array.
  4. Total bandwidth includes horizontal interface usage.
Note: For further information on the AI Engine array interface to the PL interface, see the AI Engine Array Interface Topology figure and AI Engine to PL Interface Bandwidth Performance table in the Versal Adaptive SoC AI Engine Architecture Manual (AM009).