Integrated Interface Block for Interlaken - DS959

Versal Premium Series Data Sheet: DC and AC Switching Characteristics (DS959)
Document ID
DS959
Release Date
2024-06-25
Revision
1.7 English

More information and documentation on solutions using the integrated interface block for Interlaken can be found in Versal Adaptive SoC 600G Interlaken LogiCORE IP Product Guide (PG371). The Versal Architecture and Product Data Sheet: Overview (DS950) lists how many blocks are in each Versal Premium device.

Table 1. Maximum Performance for the Interlaken Protocol
Symbol Description 1, 2 Performance as a Function of Speed Grade and Operating Voltage (VCCINT) Units
0.88V (H) 0.80V (M) 0.725V (L) 0.70V (L)
-3 -2 3 -2 -1 -2LLI -2 -1
FC0_CORE_CLK 4 Core clock 681 N/A 663 624 663 663 624 MHz
FC0_AXIS_CLK 4 AXI4-Stream interface clock 454 N/A 442 313 442 442 313 MHz
FRX_SERDES_CLK Receive serializer/deserializer clock 725.000 N/A 705.250 664.063 705.250 705.250 664.063 MHz
FTX_SERDES_CLK Transmit serializer/deserializer clock 725.000 N/A 705.250 664.063 705.250 705.250 664.063 MHz
FRX_ALT_SERDES_CLK Receive alternate serializer/deserializer clock 362.500 N/A 352.625 332.031 352.625 352.625 332.031 MHz
FTX_ALT_SERDES_CLK Transmit alternate serializer/deserializer clock 362.500 N/A 352.625 332.031 352.625 352.625 332.031 MHz
FAPB3_CLK APB3 clock 300 N/A 300 300 300 300 300 MHz
  1. Overclocked rates are supported by faster speed grade devices (-3H, -2M, -2L).
  2. These are the minimum clock frequencies at the maximum lane performance.
  3. The -2H speed grade devices do not support the 600G Interlaken protocol.
  4. FC0_CORE_CLK and FC0_AXIS_CLK are unused in FEC-only mode.