Octal-SPI device clock frequency
operating at DDR 50 MHz up to 200 MHz. |
FOSPI_CLK
|
Octal-SPI device clock frequency |
50 |
200
1
|
MHz |
FOSPI_REFCLK
|
Octal-SPI reference clock frequency |
= FOSPI_CLK
2
|
MHz |
TOSPI200IVW
|
Input valid data window |
0.5 |
– |
UI |
TOSPICKO
|
Clock to output delay, all outputs |
0.6 |
1.9 |
ns |
TOSPICSCLK
|
Chip select asserted to next clock edge |
3.375 |
– |
ns |
TOSPICLKCS
|
Clock edge to chip select deasserted |
3.375 |
– |
ns |
TOSPIDCCLK
|
Octal-SPI clock duty cycle |
45 |
55 |
% |
Octal-SPI device clock frequency
operating at SDR 50 MHz to 166 MHz. |
FOSPI_CLK
|
Octal-SPI device clock frequency |
50 |
166 |
MHz |
FOSPI_REFCLK
|
Octal-SPI reference clock frequency |
= FOSPI_CLK
2
|
MHz |
TOSPI166IVW
|
Input valid data window |
0.4 |
– |
UI |
TOSPICKO
|
Clock to output delay, all outputs |
1.8 |
3.9 |
ns |
TOSPICSCLK
|
Chip select asserted to next clock edge |
3.375 |
– |
ns |
TOSPICLKCS
|
Clock edge to chip select deasserted |
3.375 |
– |
ns |
TOSPIDCCLK
|
Octal-SPI clock duty cycle |
45 |
55 |
% |
Octal-SPI device clock frequency
operating at SDR <50 MHz. |
FOSPI_CLK
|
Octal-SPI device clock frequency |
– |
50 |
MHz |
FOSPI_REFCLK
|
Octal-SPI reference clock frequency |
4 × FOSPI_CLK
|
200 |
MHz |
TOSPIDCK
|
Setup time, all inputs |
11 |
– |
ns |
TOSPICKD
|
Hold time, all inputs |
1.0 |
– |
ns |
TOSPICKO
|
Clock to output delay, all outputs |
2.0 |
18 |
ns |
TOSPICSCLK
|
Chip select asserted to next clock edge |
3.375 |
– |
ns |
TOSPICLKCS
|
Clock edge to chip select deasserted |
3.375 |
– |
ns |
TOSPIDCCLK
|
Octal-SPI clock duty cycle |
45 |
55 |
% |
- The test conditions are
configured for the Octal-SPI interface with a 12 mA drive strength, fast slew
rate, and 12 pF load. The maximum Octal-SPI device clock frequency under different
load conditions are 166 MHz for a 20 pF load and 100 MHz for a 40 pF load.
- The Octal-SPI reference clock frequency
must be equal to FOSPI_CLK when the Octal-SPI device
clock frequency is ≥50 MHz.
|