| SPI Master Interface |
| FMSPI_CLK
|
SPI master device clock frequency (MIO) |
– |
50 |
MHz |
| SPI master device clock frequency (EMIO) |
– |
25 |
MHz |
| FSPI_REFCLK
|
SPI reference clock frequency |
– |
200 |
MHz |
| TDCMSPICLK
|
SPI master mode clock duty cycle |
45 |
55 |
% |
| TMSPISSSCLK
|
Master select asserted to first active clock edge
2
|
1 |
– |
SPI_REFCLK cycles |
| TMSPISCLKSS
|
Last active clock edge to slave select deasserted
2
|
1 |
– |
SPI_REFCLK cycles |
| TMSPIDCK
|
Input setup time for master in/slave out (MISO) |
9.9 |
– |
ns |
| TMSPICKD
|
Input hold time for MISO |
0.0 |
– |
ns |
| TMSPICKO
|
Master out/slave in (MOSI) and slave select clock-to-out
delay |
–3.7 |
5.0 |
ns |
| SPI Slave Interface |
| FSSPI_CLK
|
SPI slave device clock frequency |
– |
25 |
MHz |
| FSPI_REFCLK
|
SPI reference clock frequency |
– |
200 |
MHz |
| TSSPISSSCLK
|
Slave select asserted to first active clock edge |
1 |
– |
SPI_REFCLK cycles |
| TSSPISCLKSS
|
Last active clock edge to slave select deasserted |
1 |
– |
SPI_REFCLK cycles |
| TSSPIDCK
|
Input setup time for MISO |
5.0 |
– |
ns |
| TSSPICKD
|
Input hold time for MISO |
5.0 |
– |
ns |
| TSSPICKO
|
MOSI clock-to-out delay |
0.0 |
13 |
ns |
- The test conditions are
configured to the LVCMOS 3.3V I/O standard with a 12 mA drive strength, fast slew
rate, and 15 pF load.
- The test conditions use the SPI delay
register where XSPIPS_DR_OFFSET[xspips_dr_init_mask] = 2 and
XSPIPS_DR_OFFSET[xspips_dr_after_mask] = 2.
|