PMC eMMC Controller Interface

Versal Premium Series Data Sheet: DC and AC Switching Characteristics (DS959)

Document ID

DS959

Release Date

2024-06-25

Revision

1.7 English

Table 1. eMMC Controller Interface
Symbol	Description¹	Min	Max	Units
eMMC Interface Standard Mode
F_EMMCSCLK	eMMC standard device clock frequency²	–	25	MHz
T_DCEMMCCLK	eMMC clock duty cycle	45	55	%
T_EMMCCKO	Clock to output delay, all outputs	–2.0	4.5	ns
T_EMMCDCK	Input setup time, all inputs	2.0	–	ns
T_EMMCCKD	Input hold time, all inputs	2.0	–	ns
eMMC Interface High-speed SDR Mode
F_EMMCSDRCLK	eMMC high-speed SDR device clock frequency	25	50	MHz
T_DCEMMCSDRCLK	eMMC high-speed SDR clock duty cycle	45	55	%
T_EMMCSDRCKO	Clock to output delay, all outputs³	3.2	16.8	ns
T_EMMCSDRDIVW	Input valid data window⁴	0.4	–	UI
eMMC Interface High-speed DDR Mode
F_EMMCDDRCLK	eMMC high-speed DDR device clock frequency	25	50	MHz
T_DCEMMCDDRCLK	eMMC high-speed DDR clock duty cycle	45	55	%
T_EMMCDDRCKO1	Data clock to output delay³	2.7	7.3	ns
T_EMMCDDRDIVW	Input valid data window⁴	0.35	–	UI
T_EMMCDDRCKO2	Command clock to output delay	3.2	16	ns
T_EMMCDDRDCK2	Command input setup time	3.9	–	ns
T_EMMCDDRCKD2	Command input hold time	2.5	–	ns
eMMC Interface HS200 Mode
F_EMMCHS200CLK	eMMC HS200 device clock frequency	25	200	MHz
T_{DCEMMCHS200CLK}	eMMC HS200 clock duty cycle	30	70	%
T_EMMCHS200CKO	Clock to output delay, all outputs³	1.0	3.4	ns
T_{EMMCHS200DIVW}	Input valid data window⁴	0.5	–	UI
The test condition settings for the eMMC modes are: 12 mA drive strength, fast slew rate, and a 15 pF load. The OTAP delay (OTAP_DLY[5:0] ) test condition settings are: eMMC high-speed SDR mode = `0x05`, eMMC high-speed DDR mode = `0x05`, and eMMC HS200 mode = `0x02`. EMIO is supported in the eMMC standard mode. This specification is achieved using predetermined DLL tuning. This specification is required for capturing input data using DLL tuning.