Versal Device Support - 3.0 English - PG299

DisplayPort 1.4 TX Subsystem Product Guide (PG299)
Document ID
PG299
Release Date
2022-05-04
Version
3.0 English

The DisplayPort 1.4 TX Subsystem supports Versal® devices and uses a fabric 8B10B decoder implementation instead of a Xilinx transceiver block 8B10B decoder. For Versal devices, this results in an additional clock in the subsystem. The following table provides clock frequency values.

Table 1. Link Clock for Versal Devices
Clock Formula Value
tx_lnk_clk Link Rate/16
  • 506.25 MHz for 8.1 Gb/s
  • 337.50 MHZ for 5.4 Gb/s
  • 168.75 MHz for 2.7 Gb/s
  • 101.25 MHz for 1.62 Gb/s
tx_enc_clk Link Rate/20
  • 405 MHz for 8.1 Gb/s
  • 270 MHZ for 5.4 Gb/s
  • 135 MHz for 2.7 Gb/s
  • 81 MHz for 1.62 Gb/s

The subsystem supports block automation in IPI for Versal device designs and instantiates the transceiver bridge (PHY) IP and Versal transceiver wizard IP as part of block automation.