| Subsystem IP Facts Table | |
|---|---|
| Subsystem Specifics | |
| Supported Device Family 1 |
UltraScale+™
Families
(GTHE4, GTYE4) UltraScale™ Families (GTHE3) Versal® ACAP (GTYE5) |
| Supported User Interfaces | AXI4-Stream, AXI4-Lite, Native video |
| Resources | Performance and Resource Use web page |
| Provided with Subsystem | |
| Design Files | Hierarchical subsystem packaged with DisplayPort TX core and other IP cores |
| Example Design | Vivado® IP integrator |
| Test Bench | Not Provided |
| Constraints File | IP cores delivered with XDC files |
| Simulation Model | Not Provided |
| Supported S/W Driver | Standalone, Linux 2 |
| Tested Design Flows 3 | |
| Design Entry | Vivado Design Suite |
| Simulation | For supported simulators, see the Xilinx Design Tools: Release Notes Guide. |
| Synthesis | Vivado Synthesis |
| Support | |
| Release Notes and Known Issues | Master Answer Record: 70295 |
| All Vivado IP Change Logs | Master Vivado IP Change Logs: 72775 |
| Xilinx Support web page | |
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