The DisplayPort 1.4 TX Subsystem input
data interface is always a quad pixel interface (4PPC). 4PPC is internally translated
(inside the wrapper of the DisplayPort AXI4-Stream to Video Bridge IP) into 1, 2, or 4PPC,
then given as input to DisplayPort TX IP depending on the value programmed in the
USER_PIXEL_WIDTH register at offset address 0x1B8 (from now
referred to as USER_PIXEL_WIDTH) of the DisplayPort TX IP. With the subsystem input
interface always 4PPC, the need to have an external remapper is eliminated, and a
significant improvement in resource numbers is achieved. By default, the USER PIXEL WIDTH at
offset address 0x1B8 of DisplayPort TX IP is selected based
on Pixel Frequency in the subsystem driver. The following shows the different
USER_PIXEL_WIDTH (also referred to as PPC) for each pixel frequency:
- For USER_PIXEL_WIDTH of 1, Pixel Frequency < 75 MHz
- For USER_PIXEL_WIDTH of 2, Pixel Frequency ≥ 75 and < 300 MHz
- For USER_PIXEL_WIDTH of 4, Pixel Frequency ≥ 300 MHz
0x1B8 in Table 1
.You can override this dynamically. For example, if the driver selects a value of 2 for USER_PIXEL_WIDTH as default, you can change this to 1.
As the input data interface of the subsystem is always 4PPC, valid pixels are available in pixel 0, pixel 1, pixel 2, and pixel 3 position.
The data width of the AXI4-Stream interface depends on different parameters of the core.
For RGB and YCBCR 4:4:4:4 format Pixel_Width = MAX_BPC × 3 for 4:2:2 and 4:2:0 format Pixel_Width = MAX_BPC × 2 and for Y-only Pixel_Width =
MAX_BPC.
Interface Width = Pixel Width × 4 (because
the subsystem's intput data interface is always 4.)
For example, if the system is generated with MAX_BPC equal to 16, the data width of the AXI4-Stream interface is 16 × 4 × 3 which equals 192.