| Port Name | I/O | Description |
|---|---|---|
| tx_gt_ctrl_out[31:0] | O | External Versal device PHY control
output and mapped to 0x04C AXI4-Lite register with R/W access. [0] - Reset [3:1] - Line Rate [6:4] - Lane Count [7] - Reserved [12:8] - Vswing [17:13] - Precursor [22:18] - Postcursor [31:23] - Reserved |