Transmitter Audio/Video Clock Generation - 3.0 English

DisplayPort 1.4 TX Subsystem Product Guide (PG299)

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3.0 English

The transmitter clocking architecture supports both the asynchronous and synchronous clocking modes included in the VESA DisplayPort Standard v1.4. The clocking mode is selected by way of the Stream Clock Mode register (MAIN_STREAM_MISC0 Bit[0]). When set to 1, the link and stream clock are synchronous, in which case the MVid and NVid values are a constant. In synchronous clock mode, the source core uses the MVid and NVid register values programmed by the host processor through the AXI4-Lite interface.

When the Stream Clock Mode register is set to 0, asynchronous clock mode is enabled and the relationship between MVid and NVid is not fixed. In this mode, the Source core transmits a fixed value for NVid and the MVid value provided as a part of the clocking interface.

The following figure shows a block diagram of the transmitter clock generation process.
Figure 1. Transmitter Audio/Video Clock Generation