Link Configuration Field - 3.0 English

DisplayPort 1.4 TX Subsystem Product Guide (PG299)
Document ID
PG299
Release Date
2022-05-04
Version
3.0 English
Table 1. Link Configuration Field
Offset Access Type Description
0x000 R/W

LINK_BW_SET. Main link bandwidth setting. The register uses the same values as those supported by the DPCD register of the same name in the sink device.

[7:0] - LINK_BW_SET: Sets the value of the main link bandwidth for the sink device.
  • 0x06 = 1.62 Gb/s
  • 0x0A = 2.7 Gb/s
  • 0x14 = 5.4 Gb/s
  • 0x1E = 8.1 Gb/s
0x004 R/W LANE_COUNT_SET. Sets the number of lanes used by the source in transmitting data.

[4:0] - Set to 1, 2, or 4
0x008 R/W ENHANCED_FRAME_EN

[0] - Set to 1 by the source to enable the enhanced framing symbol sequence.
0x00C R/W

TRAINING_PATTERN_SET. Sets the link training mode.

[2:0] - Set the link training pattern according to the 2-bit code.
  • 000 = Training off
  • 001 = Training pattern 1, used for clock recovery
  • 010 = Training pattern 2, used for channel equalization
  • 011 = Training pattern 3, used for channel equalization
  • 111 = Training pattern 4, used for channel equalization
0x010 R/W

LINK_QUAL_PATTERN_SET. Transmit the link quality pattern.

[2:0] - Enable transmission of the link quality test patterns.
  • 000 = Link quality test pattern not transmitted
  • 001 = D10.2 test pattern (unscrambled) transmitted
  • 010 = Symbol Error Rate measurement pattern
  • 011 = PRBS7 transmitted
  • 100 = Custom 80-bit pattern
  • 101 = HBR2 compliance pattern
0x014 R/W SCRAMBLING_DISABLE. Set to 1 when the transmitter has disabled the scrambler and transmits all symbols.

[0] - Disable scrambling.
0x01C WO

SOFTWARE_RESET. Reads return zeros.

[0] - Soft Video Reset: When set, video logic is reset (stream 1).

[7] - AUX Soft Reset. When set, AUX logic is reset.
0x020 R/W Custom 80-bit quality pattern Bits[31:0]
0x024 R/W Custom 80-bit quality pattern Bits[63:32]
0x028 R/W [31:16] - Reserved

[15:0] - Customer 80-bit quality pattern Bits[79:64]