This section contains debugging steps for issues with data appearing to be misaligned or shifted on the monitor.
- Check the EDID timings to verify they are within the CVT standard RB and RB2 reduced blanking resolutions.
- Using EDID timings outside of the CVT standard can cause timing issues.
To fix this, define VTC_ADJUST_FOR_BS_TIMING in the xdptxss_vtc.c. This moves the BS symbol into the front porch to fix a swing in the BS timing caused by a non-standard CVT timing.