Core Enables - 3.0 English

DisplayPort 1.4 TX Subsystem Product Guide (PG299)

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3.0 English
Table 1. Core Enables
Offset Access Type Description
0x080 R/W TRANSMITTER_ENABLE. Enable the basic operations of the transmitter.

[0] - When set to 1, stream transmission is enabled. When set to 0, all lanes of the main link output stuffing symbols.

0x084 R/W MAIN_STREAM_ENABLE. Enable the transmission of main link video information.

[0] - When set to 0, the active lanes of the DisplayPort transmitter outputsW only VB-ID information with the NoVideo flag set to 1.

Note: Main stream enable/disable functionality is gated by the VSYNC input. The values written in the register are applied at the video frame boundary only.
0x0C0 WO FORCE_SCRAMBLER_RESET. Reads from this register always return 0x0.

[0] - 1 forces a scrambler reset.

0x0D0 R/W TX_MST_CONFIG: MST Configuration.

[0] – MST Enable: Set to 1 to enable MST functionality.

[1] – VC Payload Updated in sink: This is an WO bit. Set to 1 after reading DPCD register 0x2C0 (bit 0) is set.