AXI4-Lite Interface - 3.0 English

DisplayPort 1.4 TX Subsystem Product Guide (PG299)

Document ID: PG299
Release Date: 2022-05-04
Version: 3.0 English

Table 1. AXI4-Lite Interface
Port Name	I/O	Description
s_axi_aclk	I	AXI Bus clock
s_axi_aresetn	I	AXI reset. Active-Low.
s_axi_awadd[18:0]	I	Write address
s_axi_awpro[2:0]	I	Protection Type
s_axi_awvalid	I	Write address Valid
s_axi_awready	O	Write address Ready
s_axi_wdata[31:0]	I	Write data
s_axi_wstrb[3:0]	I	Write Strobe
s_axi_wvalid	I	Write data valid
s_axi_wready	O	Write data ready
s_axi_bresp[1:0]	O	Write response
s_axi_bvalid	O	Write response valid
s_axi_bready	I	Write response ready
s_axi_araddrs_axi_araddr[18:0]	I	Read address
s_axi_arprot[2:0]	I	Read protection type
s_axi_arvalid	I	Read address valid
s_axi_arready	O	Read address ready
s_axi_rdata[31:0]	O	Read data
s_axi_rresp[1:0]	O	Read data response
s_axi_rvalid	O	Read data valid
s_axi_rready	I	Read data ready