Constraining the Subsystem - 3.0 English

Required Constraints

This section is not applicable for this IP subsystem.

Device, Package, and Speed Grade Selections

See IP Facts in the related information below for details about supported devices.

This section is not applicable for this IP subsystem.

Clock Frequencies

See Clocking for more details about clock frequencies. For more information on GT clocking, see the Video PHY Controller LogiCORE IP Product Guide (PG230).

Clock Management

This section is not applicable for this IP subsystem.

Clock Placement

This section is not applicable for this IP subsystem.

Banking

For more information on the specific banking constraints, see the Video PHY Controller LogiCORE IP Product Guide (PG230).

Transceiver Placement

For more information on the specific transceiver placement constraints, see the Video PHY Controller LogiCORE IP Product Guide (PG230).

I/O Standard and Placement

This section is not applicable for this IP subsystem.

AUX Channel

The VESA DisplayPort Standard (VESA website) describes the AUX channel as a bidirectional LVDS signal. You should design the board as recommended by the VESA DP Protocol Standard. For reference, see the example design XDC file.

For UltraScale+™ and UltraScale™ families supporting HR IO banks, use the following Source constraints:

set_property IOSTANDARD LVDS_25 [get_ports aux_tx_io_p]
set_property IOSTANDARD LVDS_25 [get_ports aux_tx_io_n]

For UltraScale+ and UltraScale families supporting HP IO banks, use the following Source constraints:

set_property IOSTANDARD LVDS [get_ports aux_tx_io_p]
set_property IOSTANDARD LVDS [get_ports aux_tx_io_n]

For Versal® devices, use the following constraints:

set_property IOSTANDARD LVCMOS15 [get_ports aux_tx_io_p]
set_property IOSTANDARD LVCMOS15 [get_ports aux_tx_io_n]

HPD

The HPD signal can operate in either a 3.3V, 2.5V, or 1.5V I/O bank. By definition in the standard, it is a 3.3V signal.

For UltraScale+ and UltraScale families supporting HR IO banks, use the following constraints:

set_property IOSTANDARD LVCMOS25 [get_ports hpd]

For UltraScale+ and UltraScale families supporting HP IO banks, use the following constraints:

set_property IOSTANDARD LVCMOS18 [get_ports hpd]

For Versal devices, use the following constraints:

set_property IOSTANDARD LVCMOS15 [get_ports hpd]

Board design and connectivity should follow DisplayPort standard recommendations with proper level shifting.