XCI Inferencing - 2022.2 English

Vivado Design Suite User Guide: Designing IP Subsystems Using IP Integrator (UG994)

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2022.2 English

In some cases, a user code might have commonly-used Xilinx® IP instantiated within their RTL. The Reference RTL Module feature allows inferencing the XCI (.xci) files for IP embedded within the RTL code.

While a majority of the IP are supported for inferencing, there are a few IPs that are not supported to be inferenced within the RTL flow. To obtain the list of IPs that supports inferencing, open the project with a specified device and look for the SUPPORTS_MODREF property on the IP definition as shown below.

get_property SUPPORTS_MODREF [get_ipdefs <VLNV>]

If an unsupported IP is instantiated within the RTL code, then the Add Module command will fail with the following error:

ERROR: [filemgmt 56-181] Reference '<targetName> contains sub-design file '<xciFile>'. This sub-design is not allowed in the reference due to following reason(s): The <vlnv> core does not support module reference.

As an example, the code snippet, shown in the following figure, shows that an ILA was instantiated within the RTL code.

Figure 1. ILA IP Instantiated in RTL

The ILA IP is configured and added to the project as shown below:

Figure 2. ILA IP Configured and Added to Project

This RTL can then be added to the block design as an RTL module. It looks like the following figure.

Figure 3. RTL with ILA IP Instantiated as a Module Reference in BD