Creating a Flow in Non-Project Mode - 2022.2 English

Vivado Design Suite User Guide: Designing IP Subsystems Using IP Integrator (UG994)

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2022.2 English

The recommended approach for running non-project mode is to launch the Vivado® Design Suite in Tcl mode, or to create a Tcl script and run the tool in batch mode, using the following command:

% vivado -mode batch -source non_project_script.tcl

In non-project mode, set your project options as follows:

set_part <part_name>
set_property TARGET_LANGUAGE <VHDL/Verilog> [current_project]
set_property BOARD_PART <board_part_name> [current_project]
set_property DEFAULT_LIB work [current_project]

In non-project mode, there is no project file saved to disk. Instead, an in-memory Vivado project is created. The device/part/target-language of a block design is not stored as a part of the block design sources. The set_part command creates an in-memory project for a non-project based design, or assigns the part to the existing in-memory project.

After the in-memory project has been created, the source file (.bd) for the block design can be added to the design. This step assumes that the block design has already been created and will be reused in the non-project flow. For information on how to create a block design, see Creating a Block Design and Using Tcl Scripts to Create Projects and Block Designs.

Adding a block design to the in-memory project can be done in two different ways:

  • First, assuming that there is an existing block design with the output products generated and intact, you can add the block design using the read_bd Tcl command as follows:
    read_bd <path to the bd file>
    Note: If the block design is not generated then you will need to generate the output products for the block design by adding the following commands:
    set_property synth_checkpoint_mode None [get_files <path to the bd file>]
    generate_target all [get_files <path to the bd file>]
    read_bd <path to the bd file>
    The settings (board, part, and user repository) of the new design must match the settings of the original block design, or the IP in the block design will be locked. The settings of the new design BD must match the settings of the original block design.

    After the block design is added successfully, you need to add your top-level RTL files and any top-level XDC constraints. You will also need to instantiate the block design into your top-level RTL.

    read_verilog <top-level>.v
    read_xdc <top-level>.xdc
  • Second, you can use the block design as the top-level of the design by creating an HDL wrapper file for the block design using the following commands:
    make_wrapper -files [get_files <path to bd>/<bd instance name>.bd] -top
    read_vhdl <path to bd>/<bd instance name>_wrapper.vhd
    update_compile_order -fileset sources_1

    This creates a top-level HDL file and adds it to the source list. The top-level HDL wrapper around the block design is needed because a BD source cannot be synthesized directly.

For a MicroBlaze™ ™-based processor design, you need to add and associate an ELF with the MicroBlaze instance in the block design. This populates the block RAM initialization strings with the data from the ELF file. You can do this with the following commands:

add_files <file_name>.elf
set_property SCOPED_TO_CELLS {microblaze_0} [get_files <file_name>.elf]
set_property SCOPED_TO_REF {<bd_instance_name>} [get_files <file_name>.elf]
Tip: With the ELF file added to the project, and associated with the processor, the Vivado tools automatically merges the Block RAM memory information (MMI file) and the ELF file contents with the device bitstream (BIT) when generating the bitstream to program the device.

You can also merge the MMI, ELF, and BIT files after the bitstream has been generated by using the updatemem utility. See this link in the Vivado Design Suite User Guide: Embedded Processor Hardware Design (UG898) for more information.

If the design has multiple levels of hierarchy, you need to ensure that the correct hierarchy is provided. After this, go through the usual synthesis, place, and route steps to implement the design.

synth_design -top <top module name>
write_bitstream <bitstream file name>

To export the implemented hardware system to the Vitis™ environment, use the following command:

write_hw_platform -fixed -force  -file <path_to_xsa>/<xsa_name>.xsa

You can click the blue, underlined command links to see the write_hw_platform or write_hwdef commands in the Vivado Design Suite Tcl Command Reference Guide (UG835) for more information on the Tcl commands.