BDC Limitations - 2022.2 English

Vivado Design Suite User Guide: Designing IP Subsystems Using IP Integrator (UG994)

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2022.2 English
  • If you add a BDC interface which breaks AXI interconnect cascading, it could cause parameter propagation errors during validation.
  • Prior to creating the BDC, first instantiate an AXI clock converter or AXI register slice between the two cascaded interconnects (outside of the hierarchy). When using the same BD as a source in multiple BDCs, manually specify Apertures on each BDC boundary to avoid addressing errors.
  • When using multiple variants in the same BDC, and manually specified Apertures on the BDC boundary, validate the design with the validate_bd_design -assign_dfx_addressing option.
  • Once your BDC is locked, do not change the boundary of any source BD to avoid downstream tool errors.