You can change different aspects of the block design in the GUI environment make it easier to view the block design in the design canvas. Several options are provided as a part of the General settings to control objects that are displayed in the design canvas.
- Show hierarchy navigation bar
- Selecting this option shows all the hierarchical blocks present in the
current block design. Selecting any of the available hierarchies opens up the
hierarchy in a separate block design view.Figure 2. Showing Hierarchy Navigation Bar
Selecting the highlighted hierarchy in the previous figure, opens the hierarchy in a separate block design view.
Figure 3. Opening the Hierarchy in a Separate Block Design - Allow drag and drop of pinned objects
- This option allows you to optimize the placement of block design objects, even when they are pinned to certain locations by moving them.
- Adjust pins to reduce jogs for connections
- Selecting this option adjusts the pins of a cell on the block
design to reduce jogs in the nets. As an example, the following figure shows the
net connections between IP prior to selecting this option, and shows how the
pins are moved on the cell to optimize the routing of nets.Figure 4. Adjusting Pins to Reduce Jogs
- Move pins to avoid loops for connections
- This option allows for moving pins on either side of the symbol
to avoid any loopbacks that might be present in net routing. As an example the
following figure shows the highlighted net both before and after this option is
selected.Figure 5. Moving Pins to Avoid Loopbacks
- Group Connections
- Enable this option (in combination) using the
Match pin direction
andMatch pin type
options. It groups interfaces and pins to simplify the routing of nets in the block design canvas. The groups are auto-named by the tool as in group_1, group_2, etc. To see which pins are included as part of the group of signals, select a group pin and then view the Pin Group Properties window.Figure 6. Grouping Pins- Match pin direction
- When this option is selected (in combination with
the
Group connections
option), input pins are connected to output pins between the two endpoints. - Match pin type
- When this option is selected (in combination with
the
Group connections
option) similar types of pins such as clock, reset, interrupt, etc. are grouped together.
- Elide long text
- Selecting this option truncates the text of certain objects such as
pin/port names of cell instance names. In the example shown below, the instance
of the AXI Uartlite IP has been changed to
my_uartlite_with_really_long_name_abcdefgh
. Likewise the Interface Port connected to the interface pin/axi_ethernet_0/mdio
has been changed tomdio_mdc_asdfasdfasdfasdfasdfasdfsadfsadfasdfasdfsd
. These two objects have been truncated to...rtlite_with_really_long_name_abcdefgh
and...sdfasdfasdfasdfasdfa
as shown in the following figure.Figure 7. Eliding Text - Display function on output pins
- On certain IP such as the Concat and Slice, it could be useful
to display the bits of a bus being concatenated or ripped. Selecting this option
enables the output pins to show the resulting function as illustrated by the
following examples.
- Evaluated functions on output pins
- Select this option (in conjunction with
Display function on output pins
) to see the full function being evaluated.
Enable the output pin of the Concat IP, to display the Concat values. For example, Concat IP blocks are being used to drive a Multiplier IP in the following figure.
Figure 8. Concat IP ExampleAs you can see, the multiplier,
mult_gen_0
, has two inputsA
andB
, which are both 16-bits wide. The Concat IPxlconcat_0
andxlconcat_1
instances drive the 16 bits out on the output pindout[15:0]
. Thedout[15:0]
pin on thexlconcat_0
instance concatenates two inputsIn0_0[1:0]
andIn1_0[13:0]
. This concatenated value can be seen on the output pin of thexlconcat_0
blockdout[15:0]
. Similarly, thexlconcat_1
instance concatenated value can be seen on the output pindout[15:0]
.Note: The evaluated functions cannot be displayed on the output pin until connectivity of the output pin is made to a destination pin on the design.The output pin of the Slice IP, can be enabled to display the bits being ripped off from a bus. As a simple illustration Slice IP blocks are being used to drive the input pins of a Adder/Subtractor IP.
Figure 9. Slice IP ExampleAs you can see, the Adder/Subtractor IP,
c_addsub_0
, has two inputsA
andB
, which are both 16-bits wide. The Slice IPxslice_0
andxslice_1
instances drive the 16 bits out on the output pinDout[15:0]
. Thedout[15:0]
pin on thexslice_0
instance rips 16 bits [bits 15 through bit 0], off of the 32-bit input butsDin0_0[31:0]
. This "ripped-off" value can be seen on the output pin of thexlslice_0
blockdout[15:0]
as Dout=Din_1[15:0]. Similarly, the ripped output ofxlslice_1
instance, Dout=Din_0[17:2], can be seen on the output pindout[15:0]
.Note: The evaluated functions cannot be displayed on the output pin until connectivity of the output pin is made to a destination pin on the design. - Show blocks without interfaces
- Selecting this option displays all the cells (or blocks) on the
design canvas even if they do not have any interface pin(s) on their I/O.Note: Unselecting this option will make the blocks without any interfaces "disappear" from the block design canvas. This is a visual only representation. In reality those blocks are still present in the block design - they just "disappear" from the block design canvas to show an uncluttered view.
- Show objects with no visible connections
- This option shows or hides the following objects on the block
design canvas.
- blocks
- sub-blocks
- external ports
- block pins