Creating a Design with CIPS IP - 2022.2 English

Vivado Design Suite User Guide: Designing IP Subsystems Using IP Integrator (UG994)

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2022.2 English

Control, Interface, and Processing System (CIPS) IP allows you to configure various parts of the Versal ACAP processing system (PS), platform management controller (PMC), SysMon, and PCIe CPM blocks. CIPS IP must be included in every Versal ACAP design. Even if the PS portion of the CIPS IP is not used in the design, the PMC portion of the CIPS IP is required to boot the device. Because CIPS IP is only available in IP integrator, you must configure and instantiate this block in the IP integrator.

Note: Only a single CIPS IP is allowed per design.

In the IP integrator, CIPS IP provides optional assistance to you with block automation and board automation. Block automation provides an initial configuration and connects to additional related IP blocks. Board automation applies a specific configuration preset to CIPS IP when a board part is chosen and has a preset. In addition, other IP might provide connection automation for additional peripheral/connectivity to be connected to CIPS IP. Following are some of the automation limitations:

  • Block automation is not re-entrant. It cannot be invoked twice unless the IP is removed from the IP integrator canvas and added again.
  • Block, board, and connection automation are independent activities in the IP integrator. Using multiple automation iterations might cause conflicts.
  • Connection automation might not recognize hardened interfaces.

For descriptions of the PMC and PS, see the Versal ACAP Technical Reference Manual (AM011). For information on CIPS IP, see the Control, Interface and Processing System LogiCORE IP Product Guide (PG352). For information on the CPM, see the Versal ACAP CPM CCIX Architecture Manual (AM016), Versal ACAP CPM Mode for PCI Express Product Guide (PG346), and Versal ACAP CPM DMA and Bridge Mode for PCI Express Product Guide (PG347).