| 10/19/2022 version 2022.2 |
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Versal Designs with IP Integrator
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Added new chapter |
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Paths
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Added a new section |
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Configuring Block Design Containers from Top BD
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Updated section |
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Downloading Board Files from GitHub Using the Vivado
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Updated the section |
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Selecting a Target Board
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Updated the section |
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Limitations of the Module Reference Feature
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Updated the section |
| 04/20/2022 Version
2022.1 |
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Using the Generate Output Products Dialog Box
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Updated a figure. |
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Resource Estimation in Block Design
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Added new section. |
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Modular Design with Block Design Containers
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Removed a note. |
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Applying Changes to Block Design Containers
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Added to the note. |
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BDC Limitations
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Added new section. |
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Generating Output Products
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Updated a figure. |
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Creating a Flow in Non-Project Mode
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Added to the CAUTION note. |
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Selectively Upgrading IP Flow in Project Mode
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Updated a figure. |
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Limitations of Selectively Upgrading IP in Block Designs
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Updated a figure. |
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Referencing a Module
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Updated the section. |
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XCI Inferencing
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Updated the section. |
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Inferring Control Signals in a RTL Module
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Updated the section. |
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X_MODULE_SPEC Attribute
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Added new section. |
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Limitations of the Module Reference Feature
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Updated the section. |