Debugging IP Integrator Designs - 2022.2 English

Vivado Design Suite User Guide: Designing IP Subsystems Using IP Integrator (UG994)

Document ID
Release Date
2022.2 English

In-system debugging lets you debug your design in real-time on your target hardware. This is an essential step in design completion. Invariably, one comes across a situation which is extremely hard to replicate in a simulator. Therefore, there is a need to debug the problem in the FPGA. In this step, you place an instrument into your design with special debugging hardware to provide you with the ability to observe and control the design. After the debugging process is complete, you can remove the instrumentation or special hardware to increase performance and reduce logic.

The Vivado® IP integrator provides ways to instrument your design for debugging which is explained in the following sections:

Choosing the best flow for debugging your block design depends on your preference and the types of nets and signals that you want to debug.

As an example:

  • If you are interested in performing hardware-software co-verification using the cross-trigger feature of a MicroBlaze™ ™ or Zynq®-7000 processor, you can use the HDL Instantiation flow.
  • If you are interested in verifying interface level connectivity, then you can use the HDL Instantiation flow.
  • If you are interested in debugging the post implemented design, you can use the Netlist Insertion flow or the HDL Instantiation flow.

You can also use a combination of both flows to debug the block design and the top-level design.

Note: See the Vivado Design Suite QuickTake Video: AXI Interface Debug Using IP Integrator for information on debugging an AXI interface.