The IP packager and the Module Reference flow support a number of Attributes of
the style X_[...] that can specify a certain
behavior to replace and modify the standard interface inference heuristic. As a
global rule, the parameters always take precedence over any project-wide or
application-wide behavior. Furthermore, most attributes are attached to the ports
(because VHDL or Verilog do not have any notion of an interface that this
information could be attached to). If the attribute relates to interface-wide
information (for example, X_INTERFACE_MODE), the attribute applies to the entire
interface, and any constituent port can be chosen as representative for the whole
interface.