Referencing a Module - 2022.2 English

Vivado Design Suite User Guide: Designing IP Subsystems Using IP Integrator (UG994)

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2022.2 English

To add HDL to the block design, first you must add the RTL source file to the Vivado project. See this link in the Vivado Design Suite User Guide: System-Level Design Entry (UG895) for more information on adding design sources. Added source files show up under the Design Sources folder in the Sources window.

An RTL source file can define one or more modules or entities within the file. The module can contain one or more IP instances (support all IP types like HLS IP, IP with ELF dependencies, OOC IP, etc.) one ore more BD designs, one or more OOC/Global sources (IP or BD), and a mix of them. The Vivado IP integrator can access any of the modules defined within an added source file, as shown in the following figure.

Figure 1. RTL Sources in the Sources window

In the block design, you can add a reference to an RTL module using the Add Module command from the right-click menu of the design canvas, as shown in the following figure.

Figure 2. Add Module Command

The Add Module dialog box displays a list of all valid modules defined in the RTL source files that you have added to the project. Select a module to add from the list, and click OK to add it to the block design, shown in the following figure.

Tip: You can only select one module from the list.
Figure 3. The Add Module Dialog Box

The Add Module dialog box also provides a Hide incompatible modules check box that is enabled by default. This hides module definitions in the loaded source files that do not meet the requirements of the Module Reference feature and, consequently, cannot be added to the block design.

You can uncheck this check box to display all RTL modules defined in the loaded source files, but you will not be able to add all modules to the block design. Examples of modules that you might see when deselecting this option include:

  • Files that have syntactical errors
  • Modules with missing sources
  • Module definitions that contain or refer to an EDIF netlist, a DCP file, another block design, or unsupported IP
Hovering over an incompatible module will show a tool tip with a explanation of why the module is incompatible as shown below.
Figure 4. Incompatible Module Tool-tip
As shown, in this case the top level file for the module reference is a System Verilog file which is not supported by this feature.

The instance names of RTL modules are inferred from the top-level source of the RTL block as defined in the entity/module definition. As shown in the following figure, my_dff8_inst is the top-level entity as shown in the following code sample.

Figure 5. Inferring Module Names

Important: If the entity/module name changes in the source RTL file, the referenced module instance must be deleted from the block design and a new module added.

You can also add modules to an open block design by selecting the module in the Sources window and using the Add Module to Block Design command from the context menu, shown in the following figure.

Figure 6. Alternate Method of Adding Module from Sources Window

Finally, RTL can also be dragged and dropped from the Sources window onto the block design canvas as shown below.

Figure 7. Alternate Method of Adding Module from Sources Window

The IP integrator adds the selected module to the block design, and you can make connections to it just as you would with any other IP in the design. The IP displays in the block design with special markings that identify it as an RTL referenced module, as shown in the following figure.

Figure 8. Modules Referenced from RTL Source File

If a new block design is created after you have added design sources to the project, the block design is not set as the top-level of the design in the Sources window. The Vivado Design Suite automatically assigns a top-level module for the design as the sources are added to the project.

To set the block design as the top level of the design, right-click the block design in the Sources window and use Create HDL Wrapper. See Integrating the Block Design into a Top-Level Design for more information.

Tip: The block design cannot be directly set as the top level module.

After creating the wrapper, right-click to select it in the Sources window and use the Set as Top command from the context menu. Any RTL modules that are referenced by the block design are moved into the hierarchy of the design under the HDL wrapper, as shown in the following figure.

If you delete a referenced module from the block design, then the module is moved outside the block design hierarchy in the Sources window.

Figure 9. Referenced RTL Module Under the Block Design Tree