STARTUPE3 - 2022.2 English

Primitive: STARTUP Block

PRIMITIVE_GROUP: CONFIGURATION
PRIMITIVE_SUBGROUP: STARTUP
Families: UltraScale, UltraScale+

Introduction

This design element is used to interface device pins and logic to the global asynchronous set/reset (GSR) signal, the global 3-state (GTS) dedicated routing or the internal configuration signals or a few of the dedicated configuration pins.

Port Descriptions

Port	Direction	Width	Function
CCLK	Internal	1	Internal clock pin for timing. UltraScale+ only
CFGCLK	Output	1	Configuration main clock output.
CFGMCLK	Output	1	Configuration internal oscillator clock output.
DATA_IN<3:0>	Internal	4	Internal data pin for timing. UltraScale+ only
DATA_OUT<3:0>	Internal	4	Internal data pin for timing. UltraScale+ only
DI<3:0>	Output	4	Allow receiving on the D input pin.
DO<3:0>	Input	4	Allows control of the D pin output.
DTS<3:0>	Input	4	Allows tristate of the D pin.
EOS	Output	1	Active-High output signal indicating the End Of Startup.
FCSBO	Input	1	Controls the FCS_B pin for flash access.
FCSBTS	Input	1	Tristate the FCS_B pin.
GSR	Input	1	Global Set/Reset input (GSR cannot be used for the port).
GTS	Input	1	Global 3-state input (GTS cannot be used for the port name).
KEYCLEARB	Input	1	Clear AES Decrypter Key input from Battery-Backed RAM (BBRAM).
PACK	Input	1	PROGRAM acknowledge input.
PREQ	Output	1	PROGRAM request to fabric output.
USRCCLKO	Input	1	User CCLK input.
USRCCLKTS	Input	1	User CCLK 3-state enable input.
USRDONEO	Input	1	User DONE pin output control.
USRDONETS	Input	1	User DONE 3-state enable output.

Design Entry Method

Instantiation	Recommended
Inference	No
IP and IP Integrator Catalog	No

Available Attributes

Attribute	Type	Allowed Values	Default	Description
PROG_USR	STRING	"FALSE", "TRUE"	"FALSE"	Activate program event security feature. Requires encrypted bitstreams.
SIM_CCLK_FREQ	FLOAT(nS)	0.0 to 10.0	0.0	Set the Configuration Clock Frequency (ns) for simulation.

VHDL Instantiation Template

Unless they already exist, copy the following two statements and paste them before the entity declaration.

Library UNISIM;
use UNISIM.vcomponents.all;


-- STARTUPE3: STARTUP Block
--            UltraScale
-- Xilinx HDL Language Template, version 2022.2

STARTUPE3_inst : STARTUPE3
generic map (
   PROG_USR => "FALSE",  -- Activate program event security feature. Requires encrypted bitstreams.
   SIM_CCLK_FREQ => 0.0  -- Set the Configuration Clock Frequency (ns) for simulation.
)
port map (
   CFGCLK => CFGCLK,       -- 1-bit output: Configuration main clock output.
   CFGMCLK => CFGMCLK,     -- 1-bit output: Configuration internal oscillator clock output.
   DI => DI,               -- 4-bit output: Allow receiving on the D input pin.
   EOS => EOS,             -- 1-bit output: Active-High output signal indicating the End Of Startup.
   PREQ => PREQ,           -- 1-bit output: PROGRAM request to fabric output.
   DO => DO,               -- 4-bit input: Allows control of the D pin output.
   DTS => DTS,             -- 4-bit input: Allows tristate of the D pin.
   FCSBO => FCSBO,         -- 1-bit input: Controls the FCS_B pin for flash access.
   FCSBTS => FCSBTS,       -- 1-bit input: Tristate the FCS_B pin.
   GSR => GSR,             -- 1-bit input: Global Set/Reset input (GSR cannot be used for the port).
   GTS => GTS,             -- 1-bit input: Global 3-state input (GTS cannot be used for the port name).
   KEYCLEARB => KEYCLEARB, -- 1-bit input: Clear AES Decrypter Key input from Battery-Backed RAM (BBRAM).
   PACK => PACK,           -- 1-bit input: PROGRAM acknowledge input.
   USRCCLKO => USRCCLKO,   -- 1-bit input: User CCLK input.
   USRCCLKTS => USRCCLKTS, -- 1-bit input: User CCLK 3-state enable input.
   USRDONEO => USRDONEO,   -- 1-bit input: User DONE pin output control.
   USRDONETS => USRDONETS  -- 1-bit input: User DONE 3-state enable output.
);

-- End of STARTUPE3_inst instantiation

Verilog Instantiation Template


// STARTUPE3: STARTUP Block
//            UltraScale
// Xilinx HDL Language Template, version 2022.2

STARTUPE3 #(
   .PROG_USR("FALSE"),  // Activate program event security feature. Requires encrypted bitstreams.
   .SIM_CCLK_FREQ(0.0)  // Set the Configuration Clock Frequency (ns) for simulation.
)
STARTUPE3_inst (
   .CFGCLK(CFGCLK),       // 1-bit output: Configuration main clock output.
   .CFGMCLK(CFGMCLK),     // 1-bit output: Configuration internal oscillator clock output.
   .DI(DI),               // 4-bit output: Allow receiving on the D input pin.
   .EOS(EOS),             // 1-bit output: Active-High output signal indicating the End Of Startup.
   .PREQ(PREQ),           // 1-bit output: PROGRAM request to fabric output.
   .DO(DO),               // 4-bit input: Allows control of the D pin output.
   .DTS(DTS),             // 4-bit input: Allows tristate of the D pin.
   .FCSBO(FCSBO),         // 1-bit input: Controls the FCS_B pin for flash access.
   .FCSBTS(FCSBTS),       // 1-bit input: Tristate the FCS_B pin.
   .GSR(GSR),             // 1-bit input: Global Set/Reset input (GSR cannot be used for the port).
   .GTS(GTS),             // 1-bit input: Global 3-state input (GTS cannot be used for the port name).
   .KEYCLEARB(KEYCLEARB), // 1-bit input: Clear AES Decrypter Key input from Battery-Backed RAM (BBRAM).
   .PACK(PACK),           // 1-bit input: PROGRAM acknowledge input.
   .USRCCLKO(USRCCLKO),   // 1-bit input: User CCLK input.
   .USRCCLKTS(USRCCLKTS), // 1-bit input: User CCLK 3-state enable input.
   .USRDONEO(USRDONEO),   // 1-bit input: User DONE pin output control.
   .USRDONETS(USRDONETS)  // 1-bit input: User DONE 3-state enable output.
);

// End of STARTUPE3_inst instantiation

Related Information

See the UltraScale Architecture Configuration User Guide (UG570).