Primitive: 64-Deep by 1-Wide Static Synchronous RAM
- PRIMITIVE_GROUP: CLB
- PRIMITIVE_SUBGROUP: LUTRAM
- Families: UltraScale, UltraScale+
Introduction
This design element is a 64-bit deep by 1-bit wide static random access memory (RAM) with synchronous write capability. When the write enable is set Low, transitions on the write clock (WCLK) are ignored and data stored in the RAM is not affected. When WE is set High, any positive transition on WCLK loads the data on the data input (D) into the memory cell selected by the 6-bit address (A5:A0). This RAM block assumes an active-High WCLK. However, WCLK can be active-High or active-Low. Any inverter placed on the WCLK input net is absorbed into the block.
The signal output on the data output pin (O) is the data that is stored in the memory cell defined by the values on the address pins.
You can use the INIT attribute to specify the initial contents of the RAM. If left unspecified, the initial contents default to all zeros.
Logic Table
Mode selection is shown in the following logic table
Inputs | Outputs | ||
---|---|---|---|
WE (mode) | WCLK | D | O |
0 (read) | X | X | Data |
1 (read) | 0 | X | Data |
1 (read) | 1 | X | Data |
1 (write) | ↑ | D | D |
1 (read) | ↓ | X | Data |
Data = memory cell addressed by bits A5:A0 |
Design Entry Method
Instantiation | Yes |
Inference | Recommended |
IP Catalog | No |
Available Attributes
Attribute | Type | Allowed Values | Default | Description |
---|---|---|---|---|
INIT | HEX | Any 64-bit value | All zeros | Specifies the initial contents of the RAM. |
IS_WCLK_INVERTED | BINARY | 1'b0 to 1'b1 | 1'b0 | Specifies whether or not to use the optional inversion on the WCLK pin. |
VHDL Instantiation Template
Library UNISIM;
use UNISIM.vcomponents.all;
-- RAM64X1S: 64 x 1 positive edge write, asynchronous read single-port distributed RAM
-- UltraScale
-- Xilinx HDL Language Template, version 2022.2
RAM64X1S_inst : RAM64X1S
generic map (
INIT => X"0000000000000000", -- Initial contents of RAM
IS_WCLK_INVERTED => '0') -- Specifies active high/low WCLK
port map (
O => O, -- 1-bit data output
A0 => A0, -- Address[0] input bit
A1 => A1, -- Address[1] input bit
A2 => A2, -- Address[2] input bit
A3 => A3, -- Address[3] input bit
A4 => A4, -- Address[4] input bit
A5 => A5, -- Address[5] input bit
D => D, -- 1-bit data input
WCLK => WCLK, -- Write clock input
WE => WE -- Write enable input
);
-- End of RAM64X1S_inst instantiation
Verilog Instantiation Template
// RAM64X1S: 64 x 1 positive edge write, asynchronous read single-port
// distributed RAM (Mapped to a LUT6)
// UltraScale
// Xilinx HDL Language Template, version 2022.2
RAM64X1S #(
.INIT(64'h0000000000000000), // Initial contents of RAM
.IS_WCLK_INVERTED(1'b0) // Specifies active high/low WCLK
) RAM64X1S_inst (
.O(O), // 1-bit data output
.A0(A0), // Address[0] input bit
.A1(A1), // Address[1] input bit
.A2(A2), // Address[2] input bit
.A3(A3), // Address[3] input bit
.A4(A4), // Address[4] input bit
.A5(A5), // Address[5] input bit
.D(D), // 1-bit data input
.WCLK(WCLK), // Write clock input
.WE(WE) // Write enable input
);
// End of RAM64X1S_inst instantiation
Related Information
- See the UltraScale Architecture Configurable Logic Block User Guide (UG574).