Primitive: 18Kb FIFO (First-In-First-Out) Block RAM Memory
- PRIMITIVE_GROUP: BLOCKRAM
- PRIMITIVE_SUBGROUP: FIFO
- Families: UltraScale, UltraScale+
Introduction
The FIFO18E2 uses dedicated control logic and the 18 Kb Block RAM to deliver a configurable First-In-First-Out (FIFO) capability. This primitive can be used in a 4-bit wide by 4K deep, 9-bit wide by 2K deep, 18-bit wide by 1K deep, or a 36-bit wide by 512 deep configuration. The primitive can be configured in synchronous or dual-clock (asynchronous) mode, with all associated FIFO flags and status signals. This FIFO also features a cascade capability which lets you chain multiple FIFO18E2 components to form deeper FIFO configurations if desired.
When using the dual-clock mode with independent clocks, depending on the offset between read and write clock edges, the Empty, Almost Empty, Full, and Almost Full flags can deassert one cycle later. Due to the asynchronous nature of the clocks, the simulation model only reflects the deassertion latency cycles listed in the User Guide.
Port Descriptions
Port | Direction | Width | Function |
---|---|---|---|
Cascade Signals: Signals used when cascading more than one FIFO. | |||
CASDIN<31:0> | Input | 32 | Data input bus from previous CASDOUT bus when cascading FIFOs serially or in parallel to extend depth. Only used when CASCADE_ORDER="MIDDLE", "LAST", or "PARALLEL". |
CASDINP<3:0> | Input | 4 | Parity data input bus from previous CASDOUTP bus when cascading FIFOs serially or in parallel to extend depth. Only used when CASCADE_ORDER="MIDDLE", "LAST", or "PARALLEL". |
CASDOMUX | Input | 1 | D input to flop that drives the select line to the cascade mux on the BRAM outputs. Only used when CASCADE_ORDER="PARALLEL". |
CASDOMUXEN | Input | 1 | EN input to flop that drives the select line to the cascade mux on the BRAM outputs. Only used when CASCADE_ORDER="PARALLEL". |
CASDOUT<31:0> | Output | 32 | Data output bus to next CASDIN bus when cascading FIFOs serially or in parallel to extend depth. Only used when CASCADE_ORDER="FIRST", "MIDDLE", or "PARALLEL". |
CASDOUTP<3:0> | Output | 4 | Parity data output bus to next CASDINP bus when cascading FIFOs serially or in parallel to extend depth. Only used when CASCADE_ORDER="FIRST", "MIDDLE", or "PARALLEL". |
CASNXTEMPTY | Output | 1 | EMPTY input from previous FIFO, used for cascading FIFOs serially to extend depth. Connects to the CASNXTEMPTY of the previous FIFO. Only used when CASCADE_ORDER="MIDDLE" or "LAST". |
CASNXTRDEN | Input | 1 | RDEN input from next FIFO, used for cascading FIFOs serially to extend depth. Connects to CASPRVRDEN of the next FIFO. Only used when CASCADE_ORDER="FIRST" or "MIDDLE". |
CASOREGIMUX | Input | 1 | D input to flop that drives the select line to the cascade mux before the output registers. Only used when CASCADE_ORDER="PARALLEL" and REGISTER_MODE="DO_PIPELINED". |
CASOREGIMUXEN | Input | 1 | EN input to flop that drives the select line to the cascade mux before the output registers. Only used when CASCADE_ORDER="PARALLEL" and REGISTER_MODE="DO_PIPELINED". |
CASPRVEMPTY | Input | 1 | EMPTY input from previous FIFO, used for cascading FIFOs serially to extend depth. Connects to the CASNXTEMPTY of the previous FIFO. Only used when CASCADE_ORDER is "MIDDLE" or "LAST". |
CASPRVRDEN | Output | 1 | Control output driving the RDEN input of the previous (PRV) FIFO, used for cascading FIFOs serially to extend depth. Connects to CASNXTRDEN of the previous FIFO. Only used when CASCADE_ORDER is "MIDDLE" or "LAST". |
Read Control Signals: Read clock, enable, and reset input signals. | |||
RDCLK | Input | 1 | Read clock. |
RDEN | Input | 1 | Active-High read enable. |
REGCE | Input | 1 | Active-High enable for output register stage. |
RSTREG | Input | 1 | Active-High enable for output register reset. |
SLEEP | Input | 1 | Dynamic shut down power saving. If SLEEP is High, the block is in power saving mode. If SLEEP_ASYNC=FALSE, synchronous to RDCLK, otherwise, asynchronous input. |
Read Data: Read output data. | |||
DOUT<31:0> | Output | 32 | FIFO data output bus. Synchronous to RDCLK. |
DOUTP<3:0> | Output | 4 | FIFO parity output bus. Synchronous to RDCLK. |
Status: Flags and other FIFO status outputs. | |||
EMPTY | Output | 1 | Active-High flag to indicate when the FIFO is empty. Synchronous to RDCLK. |
FULL | Output | 1 | Active-High flag to indicate when the FIFO is full. Synchronous to WRCLK. |
PROGEMPTY | Output | 1 | Programmable flag to indicate the FIFO is almost empty (contains less than or equal to the number of words specified by the PROG_EMPTY_THRESH). Synchronous to RDCLK. |
PROGFULL | Output | 1 | Programmable flag to indicate the FIFO is almost full (contains greater than or equal to the number of words specified by the PROG_FULL_THRESH) Synchronous to WRCLK. |
RDCOUNT<12:0> | Output | 13 | Output of the internal FIFO read pointer, or a count of the number of words in the FIFO. Synchronous to RDCLK. Output value controlled by RDCOUNT_TYPE. |
RDERR | Output | 1 | Indicates that a read operation failed due to FIFO being EMPTY, or FIFO being in a reset condition. Synchronous to RDCLK. |
RDRSTBUSY | Output | 1 | Active-High indicator that the FIFO is currently in a reset state. Synchronous to RDCLK. |
WRCOUNT<12:0> | Output | 13 | Output of the internal FIFO write pointer, or a count of the number of words in the FIFO. Synchronous to WRCLK. Output value controlled by WRCOUNT_TYPE. |
WRERR | Output | 1 | Indicates that a write operation failed due to FIFO being FULL, or FIFO being in a reset condition. Synchronous to WRCLK. |
WRRSTBUSY | Output | 1 | Active-High indicator that the FIFO is currently in a reset state. Synchronous to WRCLK. |
Write Control Signals: Write clock and enable input signals. | |||
RST | Input | 1 | Active-High synchronous reset. Synchronous to WRCLK. |
WRCLK | Input | 1 | Write clock. |
WREN | Input | 1 | Active-High write enable. |
Write Data: Write input data. | |||
DIN<31:0> | Input | 32 | FIFO data input bus. Synchronous to WRCLK. |
DINP<3:0> | Input | 4 | FIFO parity input bus. Synchronous to WRCLK. |
Design Entry Method
Instantiation | Yes |
Inference | No |
IP and IP Integrator Catalog | Recommended |
Available Attributes
Attribute | Type | Allowed Values | Default | Description |
---|---|---|---|---|
CASCADE_ORDER | STRING | "NONE", "FIRST", "LAST", "MIDDLE", "PARALLEL" | "NONE" | Specifies use, configuration and position of the cascade feature to bind more than one FIFO18E2 together to form deeper FIFO depths. |
CLOCK_DOMAINS | STRING | "INDEPENDENT", "COMMON" | "INDEPENDENT" | Specifies whether to use a Common (synchronous operation) or Independent (asynchronous or different) clocks. |
FIRST_WORD_FALL_THROUGH | STRING | "FALSE", "TRUE" | "FALSE" | If TRUE, the first write to the FIFO will appear on DO without a first RDEN assertion. |
INIT | HEX | Any 36-bit HEX value | All zeroes | Specifies the initial value on the DO output after configuration. |
PROG_EMPTY_THRESH | DECIMAL | 1 to 8191 | 256 | Specifies the different between the write pointer (WRCOUNT) and read pointer (RDCOUNT). to trigger the PROGEMPTY output. |
PROG_FULL_THRESH | DECIMAL | 1 to 8191 | 256 | Specifies the different between the write pointer (WRCOUNT) and read pointer (RDCOUNT). to trigger the PROGFULL output. |
RDCOUNT_TYPE | STRING | "RAW_PNTR", "EXTENDED_DATACOUNT", "SIMPLE_DATACOUNT", "SYNC_PNTR" | "RAW_PNTR" | Specifies type and format for the RDCOUNT data. |
READ_WIDTH | DECIMAL | 4, 9, 18, 36 | 4 | Specifies the data width for the read-side of the FIFO. |
REGISTER_MODE | STRING | "UNREGISTERED", "DO_PIPELINED", "REGISTERED" | "UNREGISTERED" | Specifies output register mode. |
RSTREG_PRIORITY | STRING | "RSTREG", "REGCE" | "RSTREG" | Specifies whether reset or enable has priority. |
SLEEP_ASYNC | STRING | "FALSE", "TRUE" | "FALSE" | Specifies asynchronous or synchronous operation of the BRAM sleep mode. |
SRVAL | HEX | Any 36-bit HEX value | All zeroes | Specifies per-bit the polarity of the FIFO output after RST/RSTREG is asserted |
WRCOUNT_TYPE | STRING | "RAW_PNTR", "EXTENDED_DATACOUNT", "SIMPLE_DATACOUNT", "SYNC_PNTR" | "RAW_PNTR" | Specifies type and format for the WRCOUNT data. |
WRITE_WIDTH | DECIMAL | 4, 9, 18, 36 | 4 | Specifies the data width for the write-side of the FIFO. |
Programmable Inversion Attributes: Specifies whether or not to use the optional inversions on specific pins of this component to change the active polarity of the pin function. When set to 1 on a clock pin (WRCLK or RDCLK), this components clocks on the negative edge. When set to 1 on other pins, it changes the function to behave active-Low rather than active-High. For pins that are buses, the bit-width of this attribute should match that of the bit-width of the associated pins and a binary value indicates which inverters to use and which to bypass. If an external inverter is specified on one of these associated pins, the Vivado Design Suite will automatically set this attribute during the opt_design stage so that additional logic is not necessary for changing the input polarity. | ||||
IS_RDCLK_INVERTED | BINARY | 1'b0 to 1'b1 | 1'b0 | Specifies whether or not to use the optional inversion on the RDCLK pin. |
IS_RDEN_INVERTED | BINARY | 1'b0 to 1'b1 | 1'b0 | Specifies whether or not to use the optional inversion on the RDEN pin. |
IS_RST_INVERTED | BINARY | 1'b0 to 1'b1 | 1'b0 | Specifies whether or not to use the optional inversion on the RST pin. |
IS_RSTREG_INVERTED | BINARY | 1'b0 to 1'b1 | 1'b0 | Specifies whether or not to use the optional inversion on the RSTREG pin. |
IS_WRCLK_INVERTED | BINARY | 1'b0 to 1'b1 | 1'b0 | Specifies whether or not to use the optional inversion on the WRCLK pin. |
IS_WREN_INVERTED | BINARY | 1'b0 to 1'b1 | 1'b0 | Specifies whether or not to use the optional inversion on the WREN pin. |
VHDL Instantiation Template
Library UNISIM;
use UNISIM.vcomponents.all;
-- FIFO18E2: 18Kb FIFO (First-In-First-Out) Block RAM Memory
-- UltraScale
-- Xilinx HDL Language Template, version 2022.2
FIFO18E2_inst : FIFO18E2
generic map (
CASCADE_ORDER => "NONE", -- FIRST, LAST, MIDDLE, NONE, PARALLEL
CLOCK_DOMAINS => "INDEPENDENT", -- COMMON, INDEPENDENT
FIRST_WORD_FALL_THROUGH => "FALSE", -- FALSE, TRUE
INIT => X"000000000", -- Initial values on output port
PROG_EMPTY_THRESH => 256, -- Programmable Empty Threshold
PROG_FULL_THRESH => 256, -- Programmable Full Threshold
-- Programmable Inversion Attributes: Specifies the use of the built-in programmable inversion
IS_RDCLK_INVERTED => '0', -- Optional inversion for RDCLK
IS_RDEN_INVERTED => '0', -- Optional inversion for RDEN
IS_RSTREG_INVERTED => '0', -- Optional inversion for RSTREG
IS_RST_INVERTED => '0', -- Optional inversion for RST
IS_WRCLK_INVERTED => '0', -- Optional inversion for WRCLK
IS_WREN_INVERTED => '0', -- Optional inversion for WREN
RDCOUNT_TYPE => "RAW_PNTR", -- EXTENDED_DATACOUNT, RAW_PNTR, SIMPLE_DATACOUNT, SYNC_PNTR
READ_WIDTH => 4, -- 18-9
REGISTER_MODE => "UNREGISTERED", -- DO_PIPELINED, REGISTERED, UNREGISTERED
RSTREG_PRIORITY => "RSTREG", -- REGCE, RSTREG
SLEEP_ASYNC => "FALSE", -- FALSE, TRUE
SRVAL => X"000000000", -- SET/reset value of the FIFO outputs
WRCOUNT_TYPE => "RAW_PNTR", -- EXTENDED_DATACOUNT, RAW_PNTR, SIMPLE_DATACOUNT, SYNC_PNTR
WRITE_WIDTH => 4 -- 18-9
)
port map (
-- Cascade Signals outputs: Multi-FIFO cascade signals
CASDOUT => CASDOUT, -- 32-bit output: Data cascade output bus
CASDOUTP => CASDOUTP, -- 4-bit output: Parity data cascade output bus
CASNXTEMPTY => CASNXTEMPTY, -- 1-bit output: Cascade next empty
CASPRVRDEN => CASPRVRDEN, -- 1-bit output: Cascade previous read enable
-- Read Data outputs: Read output data
DOUT => DOUT, -- 32-bit output: FIFO data output bus
DOUTP => DOUTP, -- 4-bit output: FIFO parity output bus.
-- Status outputs: Flags and other FIFO status outputs
EMPTY => EMPTY, -- 1-bit output: Empty
FULL => FULL, -- 1-bit output: Full
PROGEMPTY => PROGEMPTY, -- 1-bit output: Programmable empty
PROGFULL => PROGFULL, -- 1-bit output: Programmable full
RDCOUNT => RDCOUNT, -- 13-bit output: Read count
RDERR => RDERR, -- 1-bit output: Read error
RDRSTBUSY => RDRSTBUSY, -- 1-bit output: Reset busy (sync to RDCLK)
WRCOUNT => WRCOUNT, -- 13-bit output: Write count
WRERR => WRERR, -- 1-bit output: Write Error
WRRSTBUSY => WRRSTBUSY, -- 1-bit output: Reset busy (sync to WRCLK)
-- Cascade Signals inputs: Multi-FIFO cascade signals
CASDIN => CASDIN, -- 32-bit input: Data cascade input bus
CASDINP => CASDINP, -- 4-bit input: Parity data cascade input bus
CASDOMUX => CASDOMUX, -- 1-bit input: Cascade MUX select
CASDOMUXEN => CASDOMUXEN, -- 1-bit input: Enable for cascade MUX select
CASNXTRDEN => CASNXTRDEN, -- 1-bit input: Cascade next read enable
CASOREGIMUX => CASOREGIMUX, -- 1-bit input: Cascade output MUX select
CASOREGIMUXEN => CASOREGIMUXEN, -- 1-bit input: Cascade output MUX select enable
CASPRVEMPTY => CASPRVEMPTY, -- 1-bit input: Cascade previous empty
-- Read Control Signals inputs: Read clock, enable and reset input signals
RDCLK => RDCLK, -- 1-bit input: Read clock
RDEN => RDEN, -- 1-bit input: Read enable
REGCE => REGCE, -- 1-bit input: Output register clock enable
RSTREG => RSTREG, -- 1-bit input: Output register reset
SLEEP => SLEEP, -- 1-bit input: Sleep Mode
-- Write Control Signals inputs: Write clock and enable input signals
RST => RST, -- 1-bit input: Reset
WRCLK => WRCLK, -- 1-bit input: Write clock
WREN => WREN, -- 1-bit input: Write enable
-- Write Data inputs: Write input data
DIN => DIN, -- 32-bit input: FIFO data input bus
DINP => DINP -- 4-bit input: FIFO parity input bus
);
-- End of FIFO18E2_inst instantiation
Verilog Instantiation Template
// FIFO18E2: 18Kb FIFO (First-In-First-Out) Block RAM Memory
// UltraScale
// Xilinx HDL Language Template, version 2022.2
FIFO18E2 #(
.CASCADE_ORDER("NONE"), // FIRST, LAST, MIDDLE, NONE, PARALLEL
.CLOCK_DOMAINS("INDEPENDENT"), // COMMON, INDEPENDENT
.FIRST_WORD_FALL_THROUGH("FALSE"), // FALSE, TRUE
.INIT(36'h000000000), // Initial values on output port
.PROG_EMPTY_THRESH(256), // Programmable Empty Threshold
.PROG_FULL_THRESH(256), // Programmable Full Threshold
// Programmable Inversion Attributes: Specifies the use of the built-in programmable inversion
.IS_RDCLK_INVERTED(1'b0), // Optional inversion for RDCLK
.IS_RDEN_INVERTED(1'b0), // Optional inversion for RDEN
.IS_RSTREG_INVERTED(1'b0), // Optional inversion for RSTREG
.IS_RST_INVERTED(1'b0), // Optional inversion for RST
.IS_WRCLK_INVERTED(1'b0), // Optional inversion for WRCLK
.IS_WREN_INVERTED(1'b0), // Optional inversion for WREN
.RDCOUNT_TYPE("RAW_PNTR"), // EXTENDED_DATACOUNT, RAW_PNTR, SIMPLE_DATACOUNT, SYNC_PNTR
.READ_WIDTH(4), // 18-9
.REGISTER_MODE("UNREGISTERED"), // DO_PIPELINED, REGISTERED, UNREGISTERED
.RSTREG_PRIORITY("RSTREG"), // REGCE, RSTREG
.SLEEP_ASYNC("FALSE"), // FALSE, TRUE
.SRVAL(36'h000000000), // SET/reset value of the FIFO outputs
.WRCOUNT_TYPE("RAW_PNTR"), // EXTENDED_DATACOUNT, RAW_PNTR, SIMPLE_DATACOUNT, SYNC_PNTR
.WRITE_WIDTH(4) // 18-9
)
FIFO18E2_inst (
// Cascade Signals outputs: Multi-FIFO cascade signals
.CASDOUT(CASDOUT), // 32-bit output: Data cascade output bus
.CASDOUTP(CASDOUTP), // 4-bit output: Parity data cascade output bus
.CASNXTEMPTY(CASNXTEMPTY), // 1-bit output: Cascade next empty
.CASPRVRDEN(CASPRVRDEN), // 1-bit output: Cascade previous read enable
// Read Data outputs: Read output data
.DOUT(DOUT), // 32-bit output: FIFO data output bus
.DOUTP(DOUTP), // 4-bit output: FIFO parity output bus.
// Status outputs: Flags and other FIFO status outputs
.EMPTY(EMPTY), // 1-bit output: Empty
.FULL(FULL), // 1-bit output: Full
.PROGEMPTY(PROGEMPTY), // 1-bit output: Programmable empty
.PROGFULL(PROGFULL), // 1-bit output: Programmable full
.RDCOUNT(RDCOUNT), // 13-bit output: Read count
.RDERR(RDERR), // 1-bit output: Read error
.RDRSTBUSY(RDRSTBUSY), // 1-bit output: Reset busy (sync to RDCLK)
.WRCOUNT(WRCOUNT), // 13-bit output: Write count
.WRERR(WRERR), // 1-bit output: Write Error
.WRRSTBUSY(WRRSTBUSY), // 1-bit output: Reset busy (sync to WRCLK)
// Cascade Signals inputs: Multi-FIFO cascade signals
.CASDIN(CASDIN), // 32-bit input: Data cascade input bus
.CASDINP(CASDINP), // 4-bit input: Parity data cascade input bus
.CASDOMUX(CASDOMUX), // 1-bit input: Cascade MUX select
.CASDOMUXEN(CASDOMUXEN), // 1-bit input: Enable for cascade MUX select
.CASNXTRDEN(CASNXTRDEN), // 1-bit input: Cascade next read enable
.CASOREGIMUX(CASOREGIMUX), // 1-bit input: Cascade output MUX select
.CASOREGIMUXEN(CASOREGIMUXEN), // 1-bit input: Cascade output MUX select enable
.CASPRVEMPTY(CASPRVEMPTY), // 1-bit input: Cascade previous empty
// Read Control Signals inputs: Read clock, enable and reset input signals
.RDCLK(RDCLK), // 1-bit input: Read clock
.RDEN(RDEN), // 1-bit input: Read enable
.REGCE(REGCE), // 1-bit input: Output register clock enable
.RSTREG(RSTREG), // 1-bit input: Output register reset
.SLEEP(SLEEP), // 1-bit input: Sleep Mode
// Write Control Signals inputs: Write clock and enable input signals
.RST(RST), // 1-bit input: Reset
.WRCLK(WRCLK), // 1-bit input: Write clock
.WREN(WREN), // 1-bit input: Write enable
// Write Data inputs: Write input data
.DIN(DIN), // 32-bit input: FIFO data input bus
.DINP(DINP) // 4-bit input: FIFO parity input bus
);
// End of FIFO18E2_inst instantiation
Related Information
- See the UltraScale Architecture Memory Resources User Guide (UG573).