CMACE4 - 2022.2 English

UltraScale Architecture Libraries Guide (UG974)

Document ID
UG974
Release Date
2022-10-19
Version
2022.2 English

Primitive: 100G MAC Block

  • PRIMITIVE_GROUP: ADVANCED
  • PRIMITIVE_SUBGROUP: MAC
  • Families: UltraScale+

Introduction

The 100G MAC Block provides a high-performance, low latency 100G Ethernet port that allows for a wide range of user customization and statistics gathering. It supports 1588 time stamping for one step and two step. This element is not intended to be instantiated, used, or modified outside of Xilinx-generated IP. The block is designed to be integrated with GTs and device clocking resources using fabric interconnect.

Design Entry Method

Instantiation No
Inference No
IP and IP Integrator Catalog Recommended

Related Information

  • See the UltraScale Architecture Integrated Block for 100G Ethernet Product Guide (PG165).