Primitive: BITSLICE_CONTROL for control using Native Mode
- PRIMITIVE_GROUP: I/O
- PRIMITIVE_SUBGROUP: BITSLICE
- Families: UltraScale, UltraScale+
Introduction
In native mode, the BITSLICE_CONTROL controls the clocking and characteristics of the six or seven bitslices within a nibble.
Port Descriptions
Port | Direction | Width | Function |
---|---|---|---|
CLK_FROM_EXT | Input | 1 | Inter-byte clock coming from north or south BITSLICE_CONTROL. |
CLK_TO_EXT_NORTH | Output | 1 | Inter-byte clock going to north BITSLICE_CONTROL. |
CLK_TO_EXT_SOUTH | Output | 1 | Inter-byte clock going to south BITSLICE_CONTROL. |
DLY_RDY | Output | 1 | Fixed delay calibration complete. |
DYN_DCI<6:0> | Output | 7 | Direct control of IOB DCI when using a memory interface. |
EN_VTC | Input | 1 | Enables voltage and temperature compensation when High. |
NCLK_NIBBLE_IN | Input | 1 | Intra-byte DQS strobes from other/clock control block. |
NCLK_NIBBLE_OUT | Output | 1 | Intra-byte DQS strobes/clock to other control block. |
PCLK_NIBBLE_IN | Input | 1 | Intra-byte DQS strobes/clock from other control block. |
PCLK_NIBBLE_OUT | Output | 1 | Intra-byte DQS strobes/clock to other control block. |
PHY_RDCS0<3:0> | Input | 4 | Rank select. Selects one of four ranks when using a memory interface. |
PHY_RDCS1<3:0> | Input | 4 | Rank select. Selects one of four ranks when using a memory interface. |
PHY_RDEN<3:0> | Input | 4 | Read burst enable when using a memory interface. |
PHY_WRCS0<3:0> | Input | 4 | Rank select. Selects one of four ranks when using a memory interface. |
PHY_WRCS1<3:0> | Input | 4 | Rank select. Selects one of four ranks when using a memory interface. |
PLL_CLK | Input | 1 | PLL clock input. |
REFCLK | Input | 1 | Frequency reference clock for delay control. |
RIU_ADDR<5:0> | Input | 6 | Address input for RIU. |
RIU_CLK | Input | 1 | System clock from fabric for RIU access. |
RIU_NIBBLE_SEL | Input | 1 | Nibble select to enable RIU read/write. |
RIU_RD_DATA<15:0> | Output | 16 | RIU Output Read data to the controller. |
RIU_VALID | Output | 1 | Indicates that last data written has been accepted when High. |
RIU_WR_DATA<15:0> | Input | 16 | RIU Input Write data from the controller. |
RIU_WR_EN | Input | 1 | Enables write to RIU when High. |
RST | Input | 1 | Asynchronous global reset. |
RX_BIT_CTRL_IN0<39:0> | Input | 40 | Input control and data bus from Bitslice 0. |
RX_BIT_CTRL_IN1<39:0> | Input | 40 | Input control and data bus from Bitslice 1. |
RX_BIT_CTRL_IN2<39:0> | Input | 40 | Input control and data bus from Bitslice 2. |
RX_BIT_CTRL_IN3<39:0> | Input | 40 | Input control and data bus from Bitslice 3. |
RX_BIT_CTRL_IN4<39:0> | Input | 40 | Input control and data bus from Bitslice 4. |
RX_BIT_CTRL_IN5<39:0> | Input | 40 | Input control and data bus from Bitslice 5. |
RX_BIT_CTRL_IN6<39:0> | Input | 40 | Input control and data bus from Bitslice 6. |
RX_BIT_CTRL_OUT0<39:0> | Output | 40 | Output control and data bus to Bitslice 0. |
RX_BIT_CTRL_OUT1<39:0> | Output | 40 | Output control and data bus to Bitslice 1. |
RX_BIT_CTRL_OUT2<39:0> | Output | 40 | Output control and data bus to Bitslice 2. |
RX_BIT_CTRL_OUT3<39:0> | Output | 40 | Output control and data bus to Bitslice 3. |
RX_BIT_CTRL_OUT4<39:0> | Output | 40 | Output control and data bus to Bitslice 4. |
RX_BIT_CTRL_OUT5<39:0> | Output | 40 | Output control and data bus to Bitslice 5. |
RX_BIT_CTRL_OUT6<39:0> | Output | 40 | Output control and data bus to Bitslice 6. |
TBYTE_IN<3:0> | Input | 4 | Output enable for 3-state control and WClkgen when using a memory interface. |
TX_BIT_CTRL_IN_TRI<39:0> | Input | 40 | Input control and data bus from 3-state TX_BITSLICE_TRI. |
TX_BIT_CTRL_IN0<39:0> | Input | 40 | Input control and data bus from Bitslice 0. |
TX_BIT_CTRL_IN1<39:0> | Input | 40 | Input control and data bus from Bitslice 1. |
TX_BIT_CTRL_IN2<39:0> | Input | 40 | Input control and data bus from Bitslice 2. |
TX_BIT_CTRL_IN3<39:0> | Input | 40 | Input control and data bus from Bitslice 3. |
TX_BIT_CTRL_IN4<39:0> | Input | 40 | Input control and data bus from Bitslice 4. |
TX_BIT_CTRL_IN5<39:0> | Input | 40 | Input control and data bus from Bitslice 5. |
TX_BIT_CTRL_IN6<39:0> | Input | 40 | Input control and data bus from Bitslice 6. |
TX_BIT_CTRL_OUT_TRI<39:0> | Output | 40 | Output control and data bus to 3-state TX_BITSLICE_TRI. |
TX_BIT_CTRL_OUT0<39:0> | Output | 40 | Output control and data bus to Bitslice 0. |
TX_BIT_CTRL_OUT1<39:0> | Output | 40 | Output control and data bus to Bitslice 1. |
TX_BIT_CTRL_OUT2<39:0> | Output | 40 | Output control and data bus to Bitslice 2. |
TX_BIT_CTRL_OUT3<39:0> | Output | 40 | Output control and data bus to Bitslice 3. |
TX_BIT_CTRL_OUT4<39:0> | Output | 40 | Output control and data bus to Bitslice 4. |
TX_BIT_CTRL_OUT5<39:0> | Output | 40 | Output control and data bus to Bitslice 5. |
TX_BIT_CTRL_OUT6<39:0> | Output | 40 | Output control and data bus to Bitslice 6. |
VTC_RDY | Output | 1 | PHY calibration is complete, VTC is enabled after EN_VTC is enabled. |
Design Entry Method
Instantiation | Yes |
Inference | No |
IP and IP Integrator Catalog | Yes |
Available Attributes
Attribute | Type | Allowed Values | Default | Description |
---|---|---|---|---|
DIV_MODE | STRING | "DIV2", "DIV4" | "DIV2" | Select between controller DIV2 or DIV4 mode. |
EN_CLK_TO_EXT_NORTH | STRING | "DISABLE", "ENABLE" | "DISABLE" | Enable clock forwarding to north for inter-byte clocking. |
EN_CLK_TO_EXT_SOUTH | STRING | "DISABLE", "ENABLE" | "DISABLE" | Enable clock forwarding to south for inter-byte clocking. |
EN_DYN_ODLY_MODE | STRING | "FALSE", "TRUE" | "FALSE" | Enables dynamic output delay mode when TRUE. |
EN_OTHER_NCLK | STRING | "FALSE", "TRUE" | "FALSE" |
|
EN_OTHER_PCLK | STRING | "FALSE", "TRUE" | "FALSE" |
|
IDLY_VT_TRACK | STRING | "TRUE", "FALSE" | "TRUE" | Globally enable VT tracking for input delays associated with the BITSLICE_CONTROL. |
INV_RXCLK | STRING | "FALSE", "TRUE" | "FALSE" | Invert clock path from IOB to upper RX bitslice. |
ODLY_VT_TRACK | STRING | "TRUE", "FALSE" | "TRUE" | Globally enable VT tracking for output delays associated with the BITSLICE_CONTROL. |
QDLY_VT_TRACK | STRING | "TRUE", "FALSE" | "TRUE" | Globally enable VT tracking for clock delays associated with the BITSLICE_CONTROL. |
READ_IDLE_COUNT | HEX | 6'h00 to 6'h3f | 6'h00 | Gap count between read bursts for ODT control counter |
REFCLK_SRC | STRING | "PLLCLK", "REFCLK" | "PLLCLK" | Selects the PLLCLK or REFCLK as the input clock for the delay control. REFCLK is supported only for RX_BITSLICE. |
ROUNDING_FACTOR | DECIMAL | 16, 2, 4, 8, 32, 64, 128 | 16 | Rounding factor in BISC spec. |
RX_CLK_PHASE_N | STRING | "SHIFT_0", "SHIFT_90" | "SHIFT_0" |
|
RX_CLK_PHASE_P | STRING | "SHIFT_0", "SHIFT_90" | "SHIFT_0" |
|
RXGATE_EXTEND | STRING | "FALSE", "TRUE" | "FALSE" | Reserved for use by Memory IP. Do Not Change. |
RX_GATING | STRING | "DISABLE", "ENABLE" | "DISABLE" | ENABLE/DISABLE read DQS gating. |
SELF_CALIBRATE | STRING | "ENABLE", "DISABLE" | "ENABLE" | Enable or Disable Built in Self Calibration of the nibble group controlled by the BITSLICE_CONTROL. |
SERIAL_MODE | STRING | "FALSE", "TRUE" | "FALSE" | Put BITSLICE read paths into serial mode. The input clock from the data receiver comes from an external source via a PLLE3. One example use is for SGMII. |
SIM_DEVICE | STRING | "7SERIES", "ULTRASCALE" | "ULTRASCALE" | Set the device version for simulation functionality. |
TX_GATING | STRING | "DISABLE", "ENABLE" | "DISABLE" | ENABLE/DISABLE clock gating in WClkgen. |
VHDL Instantiation Template
Unless they already exist, copy the following
two statements and paste them before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;
-- BITSLICE_CONTROL: BITSLICE_CONTROL for control using Native Mode
-- UltraScale
-- Xilinx HDL Language Template, version 2022.2
BITSLICE_CONTROL_inst : BITSLICE_CONTROL
generic map (
DIV_MODE => "DIV2", -- Controller DIV2/DIV4 mode (DIV2, DIV4)
EN_CLK_TO_EXT_NORTH => "DISABLE", -- Enable clock forwarding to north
EN_CLK_TO_EXT_SOUTH => "DISABLE", -- Enable clock forwarding to south
EN_DYN_ODLY_MODE => "FALSE", -- Enable dynamic output delay mode
EN_OTHER_NCLK => "FALSE", -- Select the NCLK from the other BITSLICE_CONTROL in the nibble
-- (FALSE, TRUE).
EN_OTHER_PCLK => "FALSE", -- Select the PCLK from the other BITSLICE_CONTROL in the nibble
-- (FALSE, TRUE).
IDLY_VT_TRACK => "TRUE", -- Enable VT tracking for input delays
INV_RXCLK => "FALSE", -- Invert clock path from IOB to upper RX bitslice
ODLY_VT_TRACK => "TRUE", -- Enable VT tracking for output delays
QDLY_VT_TRACK => "TRUE", -- Enable VT tracking for clock delays
READ_IDLE_COUNT => X"00", -- Gap count between read bursts for ODT control counter (0-3f)
REFCLK_SRC => "PLLCLK", -- Select the input clock for delay control (PLLCLK, REFCLK). REFCLK is
-- only supported for RX_BITSLICE.
ROUNDING_FACTOR => 16, -- Rounding factor in BISC spec (128-8)
RXGATE_EXTEND => "FALSE", -- Reserved for use by Memory IP. Do Not Change.
RX_CLK_PHASE_N => "SHIFT_0", -- Shift the Read CLK relative to read DQ during calibration (SHIFT_0,
-- SHIFT_90)
RX_CLK_PHASE_P => "SHIFT_0", -- Shift the Read CLK relative to read DQ during calibration (SHIFT_0,
-- SHIFT_90)
RX_GATING => "DISABLE", -- ENABLE/DISABLE read DQS gating
SELF_CALIBRATE => "ENABLE", -- Enable BISC of nibble controlled by BITSLICE_CONTROL
SERIAL_MODE => "FALSE", -- Put BITSLICE read paths into serial mode (FALSE, TRUE)
SIM_DEVICE => "ULTRASCALE_PLUS", -- Set the device version for simulation functionality (ULTRASCALE,
-- ULTRASCALE_PLUS, ULTRASCALE_PLUS_ES1, ULTRASCALE_PLUS_ES2)
TX_GATING => "DISABLE" -- ENABLE/DISABLE clock gating in WClkgen
)
port map (
CLK_TO_EXT_NORTH => CLK_TO_EXT_NORTH, -- 1-bit output: Inter-byte clock going to north
-- BITSLICE_CONTROL
CLK_TO_EXT_SOUTH => CLK_TO_EXT_SOUTH, -- 1-bit output: Inter-byte clock going to south
-- BITSLICE_CONTROL
DLY_RDY => DLY_RDY, -- 1-bit output: Fixed delay calibration complete
DYN_DCI => DYN_DCI, -- 7-bit output: Direct control of IOB DCI when using a
-- memory interface
NCLK_NIBBLE_OUT => NCLK_NIBBLE_OUT, -- 1-bit output: Intra-byte DQS strobes/clock to other
-- control block
PCLK_NIBBLE_OUT => PCLK_NIBBLE_OUT, -- 1-bit output: Intra-byte DQS strobes/clock to other
-- control block
RIU_RD_DATA => RIU_RD_DATA, -- 16-bit output: RIU Output Read data to the controller
RIU_VALID => RIU_VALID, -- 1-bit output: Last data written has been accepted when High
RX_BIT_CTRL_OUT0 => RX_BIT_CTRL_OUT0, -- 40-bit output: Output bus to Bitslice 0
RX_BIT_CTRL_OUT1 => RX_BIT_CTRL_OUT1, -- 40-bit output: Output bus to Bitslice 1
RX_BIT_CTRL_OUT2 => RX_BIT_CTRL_OUT2, -- 40-bit output: Output bus to Bitslice 2
RX_BIT_CTRL_OUT3 => RX_BIT_CTRL_OUT3, -- 40-bit output: Output bus to Bitslice 3
RX_BIT_CTRL_OUT4 => RX_BIT_CTRL_OUT4, -- 40-bit output: Output bus to Bitslice 4
RX_BIT_CTRL_OUT5 => RX_BIT_CTRL_OUT5, -- 40-bit output: Output bus to Bitslice 5
RX_BIT_CTRL_OUT6 => RX_BIT_CTRL_OUT6, -- 40-bit output: Output bus to Bitslice 6
TX_BIT_CTRL_OUT0 => TX_BIT_CTRL_OUT0, -- 40-bit output: Output bus to Bitslice 0
TX_BIT_CTRL_OUT1 => TX_BIT_CTRL_OUT1, -- 40-bit output: Output bus to Bitslice 1
TX_BIT_CTRL_OUT2 => TX_BIT_CTRL_OUT2, -- 40-bit output: Output bus to Bitslice 2
TX_BIT_CTRL_OUT3 => TX_BIT_CTRL_OUT3, -- 40-bit output: Output bus to Bitslice 3
TX_BIT_CTRL_OUT4 => TX_BIT_CTRL_OUT4, -- 40-bit output: Output bus to Bitslice 4
TX_BIT_CTRL_OUT5 => TX_BIT_CTRL_OUT5, -- 40-bit output: Output bus to Bitslice 5
TX_BIT_CTRL_OUT6 => TX_BIT_CTRL_OUT6, -- 40-bit output: Output bus to Bitslice 6
TX_BIT_CTRL_OUT_TRI => TX_BIT_CTRL_OUT_TRI, -- 40-bit output: Output bus to 3-state TX_BITSLICE_TRI
VTC_RDY => VTC_RDY, -- 1-bit output: PHY calibration is complete
CLK_FROM_EXT => CLK_FROM_EXT, -- 1-bit input: Inter-byte clock coming from north or south
-- BITSLICE_CONTROL
EN_VTC => EN_VTC, -- 1-bit input: Enables voltage and temperature compensation
-- when High
NCLK_NIBBLE_IN => NCLK_NIBBLE_IN, -- 1-bit input: Intra-byte DQS strobes from other/clock
-- control block
PCLK_NIBBLE_IN => PCLK_NIBBLE_IN, -- 1-bit input: Intra-byte DQS strobes/clock from other
-- control block
PHY_RDCS0 => PHY_RDCS0, -- 4-bit input: Rank select
PHY_RDCS1 => PHY_RDCS1, -- 4-bit input: Rank select
PHY_RDEN => PHY_RDEN, -- 4-bit input: Read burst enable when using a memory
-- interface
PHY_WRCS0 => PHY_WRCS0, -- 4-bit input: Rank select
PHY_WRCS1 => PHY_WRCS1, -- 4-bit input: Rank select
PLL_CLK => PLL_CLK, -- 1-bit input: PLL clock input
REFCLK => REFCLK, -- 1-bit input: Frequency reference clock for delay control
RIU_ADDR => RIU_ADDR, -- 6-bit input: Address input for RIU
RIU_CLK => RIU_CLK, -- 1-bit input: System clock from fabric for RIU access
RIU_NIBBLE_SEL => RIU_NIBBLE_SEL, -- 1-bit input: Nibble select to enable RIU read/write
RIU_WR_DATA => RIU_WR_DATA, -- 16-bit input: RIU Input Write data from the controller
RIU_WR_EN => RIU_WR_EN, -- 1-bit input: Enables write to RIU when High
RST => RST, -- 1-bit input: Asynchronous global reset
RX_BIT_CTRL_IN0 => RX_BIT_CTRL_IN0, -- 40-bit input: Input bus from Bitslice 0
RX_BIT_CTRL_IN1 => RX_BIT_CTRL_IN1, -- 40-bit input: Input bus from Bitslice 1
RX_BIT_CTRL_IN2 => RX_BIT_CTRL_IN2, -- 40-bit input: Input bus from Bitslice 2
RX_BIT_CTRL_IN3 => RX_BIT_CTRL_IN3, -- 40-bit input: Input bus from Bitslice 3
RX_BIT_CTRL_IN4 => RX_BIT_CTRL_IN4, -- 40-bit input: Input bus from Bitslice 4
RX_BIT_CTRL_IN5 => RX_BIT_CTRL_IN5, -- 40-bit input: Input bus from Bitslice 5
RX_BIT_CTRL_IN6 => RX_BIT_CTRL_IN6, -- 40-bit input: Input bus from Bitslice 6
TBYTE_IN => TBYTE_IN, -- 4-bit input: Output enable for 3-state control
TX_BIT_CTRL_IN0 => TX_BIT_CTRL_IN0, -- 40-bit input: Input bus from Bitslice 0
TX_BIT_CTRL_IN1 => TX_BIT_CTRL_IN1, -- 40-bit input: Input bus from Bitslice 1
TX_BIT_CTRL_IN2 => TX_BIT_CTRL_IN2, -- 40-bit input: Input bus from Bitslice 2
TX_BIT_CTRL_IN3 => TX_BIT_CTRL_IN3, -- 40-bit input: Input bus from Bitslice 3
TX_BIT_CTRL_IN4 => TX_BIT_CTRL_IN4, -- 40-bit input: Input bus from Bitslice 4
TX_BIT_CTRL_IN5 => TX_BIT_CTRL_IN5, -- 40-bit input: Input bus from Bitslice 5
TX_BIT_CTRL_IN6 => TX_BIT_CTRL_IN6, -- 40-bit input: Input bus from Bitslice 6
TX_BIT_CTRL_IN_TRI => TX_BIT_CTRL_IN_TRI -- 40-bit input: Input bus from 3-state TX_BITSLICE_TRI
);
-- End of BITSLICE_CONTROL_inst instantiation
Verilog Instantiation Template
// BITSLICE_CONTROL: BITSLICE_CONTROL for control using Native Mode
// UltraScale
// Xilinx HDL Language Template, version 2022.2
BITSLICE_CONTROL #(
.DIV_MODE("DIV2"), // Controller DIV2/DIV4 mode (DIV2, DIV4)
.EN_CLK_TO_EXT_NORTH("DISABLE"), // Enable clock forwarding to north
.EN_CLK_TO_EXT_SOUTH("DISABLE"), // Enable clock forwarding to south
.EN_DYN_ODLY_MODE("FALSE"), // Enable dynamic output delay mode
.EN_OTHER_NCLK("FALSE"), // Select the NCLK from the other BITSLICE_CONTROL in the nibble (FALSE,
// TRUE).
.EN_OTHER_PCLK("FALSE"), // Select the PCLK from the other BITSLICE_CONTROL in the nibble (FALSE,
// TRUE).
.IDLY_VT_TRACK("TRUE"), // Enable VT tracking for input delays
.INV_RXCLK("FALSE"), // Invert clock path from IOB to upper RX bitslice
.ODLY_VT_TRACK("TRUE"), // Enable VT tracking for output delays
.QDLY_VT_TRACK("TRUE"), // Enable VT tracking for clock delays
.READ_IDLE_COUNT(6'h00), // Gap count between read bursts for ODT control counter (0-3f)
.REFCLK_SRC("PLLCLK"), // Select the input clock for delay control (PLLCLK, REFCLK). REFCLK is
// only supported for RX_BITSLICE.
.ROUNDING_FACTOR(16), // Rounding factor in BISC spec (128-8)
.RXGATE_EXTEND("FALSE"), // Reserved for use by Memory IP. Do Not Change.
.RX_CLK_PHASE_N("SHIFT_0"), // Shift the Read CLK relative to read DQ during calibration (SHIFT_0,
// SHIFT_90)
.RX_CLK_PHASE_P("SHIFT_0"), // Shift the Read CLK relative to read DQ during calibration (SHIFT_0,
// SHIFT_90)
.RX_GATING("DISABLE"), // ENABLE/DISABLE read DQS gating
.SELF_CALIBRATE("ENABLE"), // Enable BISC of nibble controlled by BITSLICE_CONTROL
.SERIAL_MODE("FALSE"), // Put BITSLICE read paths into serial mode (FALSE, TRUE)
.SIM_DEVICE("ULTRASCALE_PLUS"), // Set the device version for simulation functionality (ULTRASCALE,
// ULTRASCALE_PLUS, ULTRASCALE_PLUS_ES1, ULTRASCALE_PLUS_ES2)
.TX_GATING("DISABLE") // ENABLE/DISABLE clock gating in WClkgen
)
BITSLICE_CONTROL_inst (
.CLK_TO_EXT_NORTH(CLK_TO_EXT_NORTH), // 1-bit output: Inter-byte clock going to north
// BITSLICE_CONTROL
.CLK_TO_EXT_SOUTH(CLK_TO_EXT_SOUTH), // 1-bit output: Inter-byte clock going to south
// BITSLICE_CONTROL
.DLY_RDY(DLY_RDY), // 1-bit output: Fixed delay calibration complete
.DYN_DCI(DYN_DCI), // 7-bit output: Direct control of IOB DCI when using a memory
// interface
.NCLK_NIBBLE_OUT(NCLK_NIBBLE_OUT), // 1-bit output: Intra-byte DQS strobes/clock to other control
// block
.PCLK_NIBBLE_OUT(PCLK_NIBBLE_OUT), // 1-bit output: Intra-byte DQS strobes/clock to other control
// block
.RIU_RD_DATA(RIU_RD_DATA), // 16-bit output: RIU Output Read data to the controller
.RIU_VALID(RIU_VALID), // 1-bit output: Last data written has been accepted when High
.RX_BIT_CTRL_OUT0(RX_BIT_CTRL_OUT0), // 40-bit output: Output bus to Bitslice 0
.RX_BIT_CTRL_OUT1(RX_BIT_CTRL_OUT1), // 40-bit output: Output bus to Bitslice 1
.RX_BIT_CTRL_OUT2(RX_BIT_CTRL_OUT2), // 40-bit output: Output bus to Bitslice 2
.RX_BIT_CTRL_OUT3(RX_BIT_CTRL_OUT3), // 40-bit output: Output bus to Bitslice 3
.RX_BIT_CTRL_OUT4(RX_BIT_CTRL_OUT4), // 40-bit output: Output bus to Bitslice 4
.RX_BIT_CTRL_OUT5(RX_BIT_CTRL_OUT5), // 40-bit output: Output bus to Bitslice 5
.RX_BIT_CTRL_OUT6(RX_BIT_CTRL_OUT6), // 40-bit output: Output bus to Bitslice 6
.TX_BIT_CTRL_OUT0(TX_BIT_CTRL_OUT0), // 40-bit output: Output bus to Bitslice 0
.TX_BIT_CTRL_OUT1(TX_BIT_CTRL_OUT1), // 40-bit output: Output bus to Bitslice 1
.TX_BIT_CTRL_OUT2(TX_BIT_CTRL_OUT2), // 40-bit output: Output bus to Bitslice 2
.TX_BIT_CTRL_OUT3(TX_BIT_CTRL_OUT3), // 40-bit output: Output bus to Bitslice 3
.TX_BIT_CTRL_OUT4(TX_BIT_CTRL_OUT4), // 40-bit output: Output bus to Bitslice 4
.TX_BIT_CTRL_OUT5(TX_BIT_CTRL_OUT5), // 40-bit output: Output bus to Bitslice 5
.TX_BIT_CTRL_OUT6(TX_BIT_CTRL_OUT6), // 40-bit output: Output bus to Bitslice 6
.TX_BIT_CTRL_OUT_TRI(TX_BIT_CTRL_OUT_TRI), // 40-bit output: Output bus to 3-state TX_BITSLICE_TRI
.VTC_RDY(VTC_RDY), // 1-bit output: PHY calibration is complete
.CLK_FROM_EXT(CLK_FROM_EXT), // 1-bit input: Inter-byte clock coming from north or south
// BITSLICE_CONTROL
.EN_VTC(EN_VTC), // 1-bit input: Enables voltage and temperature compensation
// when High
.NCLK_NIBBLE_IN(NCLK_NIBBLE_IN), // 1-bit input: Intra-byte DQS strobes from other/clock
// control block
.PCLK_NIBBLE_IN(PCLK_NIBBLE_IN), // 1-bit input: Intra-byte DQS strobes/clock from other
// control block
.PHY_RDCS0(PHY_RDCS0), // 4-bit input: Rank select
.PHY_RDCS1(PHY_RDCS1), // 4-bit input: Rank select
.PHY_RDEN(PHY_RDEN), // 4-bit input: Read burst enable when using a memory interface
.PHY_WRCS0(PHY_WRCS0), // 4-bit input: Rank select
.PHY_WRCS1(PHY_WRCS1), // 4-bit input: Rank select
.PLL_CLK(PLL_CLK), // 1-bit input: PLL clock input
.REFCLK(REFCLK), // 1-bit input: Frequency reference clock for delay control
.RIU_ADDR(RIU_ADDR), // 6-bit input: Address input for RIU
.RIU_CLK(RIU_CLK), // 1-bit input: System clock from fabric for RIU access
.RIU_NIBBLE_SEL(RIU_NIBBLE_SEL), // 1-bit input: Nibble select to enable RIU read/write
.RIU_WR_DATA(RIU_WR_DATA), // 16-bit input: RIU Input Write data from the controller
.RIU_WR_EN(RIU_WR_EN), // 1-bit input: Enables write to RIU when High
.RST(RST), // 1-bit input: Asynchronous global reset
.RX_BIT_CTRL_IN0(RX_BIT_CTRL_IN0), // 40-bit input: Input bus from Bitslice 0
.RX_BIT_CTRL_IN1(RX_BIT_CTRL_IN1), // 40-bit input: Input bus from Bitslice 1
.RX_BIT_CTRL_IN2(RX_BIT_CTRL_IN2), // 40-bit input: Input bus from Bitslice 2
.RX_BIT_CTRL_IN3(RX_BIT_CTRL_IN3), // 40-bit input: Input bus from Bitslice 3
.RX_BIT_CTRL_IN4(RX_BIT_CTRL_IN4), // 40-bit input: Input bus from Bitslice 4
.RX_BIT_CTRL_IN5(RX_BIT_CTRL_IN5), // 40-bit input: Input bus from Bitslice 5
.RX_BIT_CTRL_IN6(RX_BIT_CTRL_IN6), // 40-bit input: Input bus from Bitslice 6
.TBYTE_IN(TBYTE_IN), // 4-bit input: Output enable for 3-state control
.TX_BIT_CTRL_IN0(TX_BIT_CTRL_IN0), // 40-bit input: Input bus from Bitslice 0
.TX_BIT_CTRL_IN1(TX_BIT_CTRL_IN1), // 40-bit input: Input bus from Bitslice 1
.TX_BIT_CTRL_IN2(TX_BIT_CTRL_IN2), // 40-bit input: Input bus from Bitslice 2
.TX_BIT_CTRL_IN3(TX_BIT_CTRL_IN3), // 40-bit input: Input bus from Bitslice 3
.TX_BIT_CTRL_IN4(TX_BIT_CTRL_IN4), // 40-bit input: Input bus from Bitslice 4
.TX_BIT_CTRL_IN5(TX_BIT_CTRL_IN5), // 40-bit input: Input bus from Bitslice 5
.TX_BIT_CTRL_IN6(TX_BIT_CTRL_IN6), // 40-bit input: Input bus from Bitslice 6
.TX_BIT_CTRL_IN_TRI(TX_BIT_CTRL_IN_TRI) // 40-bit input: Input bus from 3-state TX_BITSLICE_TRI
);
// End of BITSLICE_CONTROL_inst instantiation
Related Information
- See the UltraScale Architecture SelectIO Resources User Guide (UG571).