Primitive: Bidirectional I/O Buffer with Offset Calibration and VREF Tuning
- PRIMITIVE_GROUP: I/O
- PRIMITIVE_SUBGROUP: BIDIR_BUFFER
- Families: UltraScale, UltraScale+
Introduction
The bidirectional input/output buffer primitive (IOBUFE3) is only supported in HP I/O banks. This primitive has functions similar to the IOBUF_DCIEN along with controls for offset calibration and VREF tuning with input buffer disable (IBUFDISABLE) and on-die input termination control (DCITERMDISABLE) for the input buffer. The offset calibration feature is accessed using the OSC_EN and OSC[3:0] ports. The VREF scan feature is accessed using the HPIO_VREF primitive in conjunction with IOBUFE3.
I/O attributes that do not impact the logic function of the component such as IOSTANDARD, DRIVE and IBUF_LOW_PWR should be supplied in XDC or to the top-level port via an appropriate property. For details on applying such properties to the associated port, see the Vivado Design Suite Properties Reference Guide (UG912).
Port Descriptions
Port | Direction | Width | Function |
---|---|---|---|
DCITERMDISABLE | Input | 1 | Control to enable/disable DCI termination. This is generally used to reduce power in long periods of an idle state. |
I | Input | 1 | Input of OBUF. Connect to the logic driving the output port. |
IBUFDISABLE | Input | 1 | Disables input path through the buffer and forces to a logic Low. This feature is generally used to reduce power at times when the I/O is idle for a period of time. |
IO | Inout | 1 | Bidirectional port to be connected directly to top-level inout port. |
O | Output | 1 | Output path of the buffer. |
OSC<3:0> | Input | 4 | Offset cancellation value |
OSC_EN | Input | 1 | Offset cancellation enable |
T | Input | 1 | 3-state enable input signifying whether the buffer acts as an input or output. |
VREF | Input | 1 | Vref input from HPIO_VREF |
Design Entry Method
Instantiation | Yes |
Inference | No |
IP and IP Integrator Catalog | No |
Available Attributes
Attribute | Type | Allowed Values | Default | Description |
---|---|---|---|---|
SIM_DEVICE | STRING | "7SERIES", "ULTRASCALE" | "ULTRASCALE" | Set the device version for simulation functionality. |
SIM_INPUT_BUFFER_OFFSET | DECIMAL | -50 to 50 | 0 | Offset value for simulation purposes. |
USE_IBUFDISABLE | STRING | "FALSE", "T_CONTROL", "TRUE" | "FALSE" | Set this attribute to "TRUE" to enable the IBUFDISABLE pin. |
VHDL Instantiation Template
Library UNISIM;
use UNISIM.vcomponents.all;
-- IOBUFE3: Bidirectional I/O Buffer with Offset Calibration and VREF Tuning
-- UltraScale
-- Xilinx HDL Language Template, version 2022.2
IOBUFE3_inst : IOBUFE3
generic map (
SIM_DEVICE => "ULTRASCALE_PLUS", -- Set the device version for simulation functionality (ULTRASCALE,
-- ULTRASCALE_PLUS)
SIM_INPUT_BUFFER_OFFSET => 0, -- Offset value for simulation (-50-50)
USE_IBUFDISABLE => "FALSE" -- Enable/Disable the IBUFDISABLE pin (FALSE, TRUE, T_CONTROL)
)
port map (
O => O, -- 1-bit output: Buffer output
DCITERMDISABLE => DCITERMDISABLE, -- 1-bit input: DCI Termination Disable
I => I, -- 1-bit input: Buffer input
IBUFDISABLE => IBUFDISABLE, -- 1-bit input: Buffer disable input, high=disable
IO => IO, -- 1-bit inout: Buffer inout (connect directly to top-level port)
OSC => OSC, -- 4-bit input: Offset cancellation value
OSC_EN => OSC_EN, -- 1-bit input: Offset cancellation enable
T => T, -- 1-bit input: 3-state enable input
VREF => VREF -- 1-bit input: Vref input from HPIO_VREF
);
-- End of IOBUFE3_inst instantiation
Verilog Instantiation Template
// IOBUFE3: Bidirectional I/O Buffer with Offset Calibration and VREF Tuning
// UltraScale
// Xilinx HDL Language Template, version 2022.2
IOBUFE3 #(
.SIM_DEVICE("ULTRASCALE_PLUS"), // Set the device version for simulation functionality (ULTRASCALE,
// ULTRASCALE_PLUS)
.SIM_INPUT_BUFFER_OFFSET(0), // Offset value for simulation (-50-50)
.USE_IBUFDISABLE("FALSE") // Enable/Disable the IBUFDISABLE pin (FALSE, TRUE, T_CONTROL)
)
IOBUFE3_inst (
.O(O), // 1-bit output: Buffer output
.DCITERMDISABLE(DCITERMDISABLE), // 1-bit input: DCI Termination Disable
.I(I), // 1-bit input: Buffer input
.IBUFDISABLE(IBUFDISABLE), // 1-bit input: Buffer disable input, high=disable
.IO(IO), // 1-bit inout: Buffer inout (connect directly to top-level port)
.OSC(OSC), // 4-bit input: Offset cancellation value
.OSC_EN(OSC_EN), // 1-bit input: Offset cancellation enable
.T(T), // 1-bit input: 3-state enable input
.VREF(VREF) // 1-bit input: Vref input from HPIO_VREF
);
// End of IOBUFE3_inst instantiation