Primitive: Advanced Mixed Mode Clock Manager (MMCM)
- PRIMITIVE_GROUP: CLOCK
- PRIMITIVE_SUBGROUP: PLL
- Families: UltraScale+
Introduction
The MMCME4 is a mixed signal block designed to support frequency synthesis, clock network deskew, and jitter reduction. The clock outputs can each have an individual divide, phase shift and duty cycle based on the same VCO frequency. The MMCME4 also supports dynamic phase shifting and fractional divides.
Port Descriptions
Port | Direction | Width | Function |
---|---|---|---|
CDDCDONE | Output | 1 | Acknowledge signal that output clock dynamic divide is done and the output is valid. |
CDDCREQ | Input | 1 | Active-High request signal for dynamically changing output clock divide. |
CLKFBIN | Input | 1 | Feedback clock pin to the MMCM. |
CLKFBOUT | Output | 1 | Dedicated MMCM Feedback clock output. |
CLKFBOUTB | Output | 1 | Inverted CLKFBOUT. |
CLKFBSTOPPED | Output | 1 | Status pin indicating that the feedback clock has stopped. |
CLKINSEL | Input | 1 | Signal controls the state of the input MUX, High = CLKIN1, Low = CLKIN2. |
CLKINSTOPPED | Output | 1 | Status pin indicating that the input clock has stopped. |
CLKIN1 | Input | 1 | Primary clock input. |
CLKIN2 | Input | 1 | Secondary clock input to dynamically switch the MMCM reference clock. |
CLKOUT0 | Output | 1 | CLKOUT0 output. |
CLKOUT0B | Output | 1 | Inverted CLKOUT0. |
CLKOUT1 | Output | 1 | CLKOUT1 output. |
CLKOUT1B | Output | 1 | Inverted CLKOUT1. |
CLKOUT2 | Output | 1 | CLKOUT2 output. |
CLKOUT2B | Output | 1 | Inverted CLKOUT2. |
CLKOUT3 | Output | 1 | CLKOUT3 output. |
CLKOUT3B | Output | 1 | Inverted CLKOUT3. |
CLKOUT4 | Output | 1 | CLKOUT4 output. |
CLKOUT5 | Output | 1 | CLKOUT5 output. |
CLKOUT6 | Output | 1 | CLKOUT6 output. |
DADDR<6:0> | Input | 7 | The dynamic reconfiguration address (DADDR) input bus provides a reconfiguration address for the dynamic reconfiguration. When not used, all bits must be assigned zeros. |
DCLK | Input | 1 | The DCLK signal is the reference clock for the dynamic reconfiguration port. |
DEN | Input | 1 | The dynamic reconfiguration enable (DEN) provides the enable control signal to access the dynamic reconfiguration feature. When the dynamic reconfiguration feature is not used, DEN must be tied Low. |
DI<15:0> | Input | 16 | The dynamic reconfiguration data input (DI) bus provides reconfiguration data. When not used, all bits must be set to zero. |
DO<15:0> | Output | 16 | The dynamic reconfiguration output bus provides MMCM data output when using dynamic reconfiguration. |
DRDY | Output | 1 | The dynamic reconfiguration ready output (DRDY) provides the response to the DEN signal for the MMCMs dynamic reconfiguration feature. |
DWE | Input | 1 | The dynamic reconfiguration write enable (DWE) input pin provides the write enable control signal to write the DI data into the DADDR address. When not used, it must be tied Low. |
LOCKED | Output | 1 | An output from the MMCM that indicates when the MMCM has achieved phase alignment within a predefined window and frequency matching within a predefined PPM range. The MMCM automatically locks after power on, no extra reset is required. LOCKED will be deasserted if the input clock stops or the phase alignment is violated (for example, input clock phase shift). The MMCM must be reset after LOCKED is deasserted. |
PSCLK | Input | 1 | Phase shift clock. |
PSDONE | Output | 1 | Phase shift done. |
PSEN | Input | 1 | Phase shift enable. |
PSINCDEC | Input | 1 | Phase shift increment/decrement control. |
PWRDWN | Input | 1 | Powers down MMCM components, thus reducing power consumption when derived clocks are not in use for sustained periods of time. Upon release of PWRDWN, the MMCM must regain LOCK before use. |
RST | Input | 1 | Asynchronous reset signal. The MMCM will synchronously re-enable itself when this signal is released (i.e., MMCM re-enabled). A reset is required when the input clock conditions change (for example, frequency). |
Design Entry Method
Instantiation | Yes |
Inference | No |
IP and IP Integrator Catalog | Recommended |
Available Attributes
Attribute | Type | Allowed Values | Default | Description |
---|---|---|---|---|
BANDWIDTH | STRING | "OPTIMIZED", "HIGH", "LOW" | "OPTIMIZED" | Specifies the MMCM programming algorithm affecting the jitter, phase margin and other characteristics of the MMCM. |
CLKFBOUT_MULT_F | 3 significant digit FLOAT | 2.000 to 128.000 | 5.000 | Specifies the amount to multiply all CLKOUT clock outputs if a different frequency is desired. This number, in combination with the associated CLKOUT#_DIVIDE value and DIVCLK_DIVIDE value, will determine the output frequency. |
CLKFBOUT_PHASE | 3 significant digit FLOAT | -360.000 to 360.000 | 0.000 | Specifies the phase offset in degrees of the clock feedback output. Shifting the feedback clock results in a negative phase shift of all output clocks to the MMCM. |
CLKFBOUT_USE_FINE_PS | STRING | "FALSE", "TRUE" | "FALSE" | Counter variable fine phase shift enable. |
CLKIN1_PERIOD | FLOAT(nS) | 0.000 to 100.000 | 0.000 | Specifies the input period to the CLKIN1 in ns. |
CLKIN2_PERIOD | FLOAT(nS) | 0.000 to 100.000 | 0.000 | Specifies the input period to the CLKIN2 in ns. |
CLKOUT0_DIVIDE_F | 3 significant digit FLOAT | 1.000 to 128.000 | 1.000 | Specifies the amount to fractional divide the associated CLKOUT clock output if a different frequency is desired. This number in combination with the CLKFBOUT_MULT_F and DIVCLK_DIVIDE values will determine the output frequency. |
CLKOUT0_DUTY_CYCLE | 3 significant digit FLOAT | 0.001 to 0.999 | 0.500 | Specifies the Duty Cycle of CLKOUT0 clock output in percentage (i.e., 0.500 will generate a 50% duty cycle). |
CLKOUT0_PHASE | 3 significant digit FLOAT | -360.000 to 360.000 | 0.000 | Specifies the phase offset in degrees of the CLKOUT0 output. |
CLKOUT0_USE_FINE_PS | STRING | "FALSE", "TRUE" | "FALSE" | Counter variable fine phase shift enable. |
CLKOUT1_DIVIDE | DECIMAL | 1 to 128 | 1 | Specifies the amount by which to divide CLKOUT1 to create a different frequency. |
CLKOUT1_DUTY_CYCLE | 3 significant digit FLOAT | 0.001 to 0.999 | 0.500 | Specifies the duty cycle for CLKOUT1. |
CLKOUT1_PHASE | 3 significant digit FLOAT | -360.000 to 360.000 | 0.000 | Specifies the phase offset for CLKOUT1. |
CLKOUT1_USE_FINE_PS | STRING | "FALSE", "TRUE" | "FALSE" | Counter variable fine phase shift enable. |
CLKOUT2_DIVIDE | DECIMAL | 1 to 128 | 1 | Specifies the amount by which to divide CLKOUT2 to create a different frequency. |
CLKOUT2_DUTY_CYCLE | 3 significant digit FLOAT | 0.001 to 0.999 | 0.500 | Specifies the duty cycle for CLKOUT2. |
CLKOUT2_PHASE | 3 significant digit FLOAT | -360.000 to 360.000 | 0.000 | Specifies the phase offset for CLKOUT2. |
CLKOUT2_USE_FINE_PS | STRING | "FALSE", "TRUE" | "FALSE" | Counter variable fine phase shift enable. |
CLKOUT3_DIVIDE | DECIMAL | 1 to 128 | 1 | Specifies the amount by which to divide CLKOUT3 to create a different frequency. |
CLKOUT3_DUTY_CYCLE | 3 significant digit FLOAT | 0.001 to 0.999 | 0.500 | Specifies the duty cycle for CLKOUT3. |
CLKOUT3_PHASE | 3 significant digit FLOAT | -360.000 to 360.000 | 0.000 | Specifies the phase offset for CLKOUT3. |
CLKOUT3_USE_FINE_PS | STRING | "FALSE", "TRUE" | "FALSE" | Counter variable fine phase shift enable. |
CLKOUT4_CASCADE | STRING | "FALSE", "TRUE" | "FALSE" | Cascades the output divider (counter) CLKOUT6 into the input of the CLKOUT4 divider for an output clock divider that is greater than 128, effectively providing a total divide value of 16,384. |
CLKOUT4_DIVIDE | DECIMAL | 1 to 128 | 1 | Specifies the amount by which to divide CLKOUT4 to create a different frequency. |
CLKOUT4_DUTY_CYCLE | 3 significant digit FLOAT | 0.001 to 0.999 | 0.500 | Specifies the duty cycle for CLKOUT4. |
CLKOUT4_PHASE | 3 significant digit FLOAT | -360.000 to 360.000 | 0.000 | Specifies the phase offset for CLKOUT4. |
CLKOUT4_USE_FINE_PS | STRING | "FALSE", "TRUE" | "FALSE" | Counter variable fine phase shift enable. |
CLKOUT5_DIVIDE | DECIMAL | 1 to 128 | 1 | Specifies the amount by which to divide CLKOUT5 to create a different frequency. |
CLKOUT5_DUTY_CYCLE | 3 significant digit FLOAT | 0.001 to 0.999 | 0.500 | Specifies the duty cycle for CLKOUT5. |
CLKOUT5_PHASE | 3 significant digit FLOAT | -360.000 to 360.000 | 0.000 | Specifies the phase offset for CLKOUT5. |
CLKOUT5_USE_FINE_PS | STRING | "FALSE", "TRUE" | "FALSE" | Counter variable fine phase shift enable. |
CLKOUT6_DIVIDE | DECIMAL | 1 to 128 | 1 | Specifies the amount by which to divide CLKOUT6 to create a different frequency. |
CLKOUT6_DUTY_CYCLE | 3 significant digit FLOAT | 0.001 to 0.999 | 0.500 | Specifies the duty cycle for CLKOUT6. |
CLKOUT6_PHASE | 3 significant digit FLOAT | -360.000 to 360.000 | 0.000 | Specifies the phase offset for CLKOUT6. |
CLKOUT6_USE_FINE_PS | STRING | "FALSE", "TRUE" | "FALSE" | Counter variable fine phase shift enable. |
COMPENSATION | STRING | "AUTO", "BUF_IN", "EXTERNAL", "INTERNAL", "ZHOLD" | "AUTO" | Clock input compensation. This should be set to AUTO. Defines how the MMCM feedback is configured.
|
DIVCLK_DIVIDE | DECIMAL | 1 to 106 | 1 | Specifies the division ratio for all output clocks with respect to the input clock. Effectively divides the CLKIN going into the PFD. |
IS_CLKFBIN_INVERTED | BINARY | 1'b0 to 1'b1 | 1'b0 | Specifies whether or not to use the optional inversion on the CLKFBIN pin. |
IS_CLKINSEL_INVERTED | BINARY | 1'b0 to 1'b1 | 1'b0 | Specifies whether or not to use the optional inversion on the CLKINSEL pin. |
IS_CLKIN1_INVERTED | BINARY | 1'b0 to 1'b1 | 1'b0 | Specifies whether or not to use the optional inversion on the CLKIN1 pin. |
IS_CLKIN2_INVERTED | BINARY | 1'b0 to 1'b1 | 1'b0 | Specifies whether or not to use the optional inversion on the CLKIN2 pin. |
IS_PSEN_INVERTED | BINARY | 1'b0 to 1'b1 | 1'b0 | Specifies whether or not to use the optional inversion on the PSEN pin. |
IS_PSINCDEC_INVERTED | BINARY | 1'b0 to 1'b1 | 1'b0 | Specifies whether or not to use the optional inversion on the PSINCDEC pin. |
IS_PWRDWN_INVERTED | BINARY | 1'b0 to 1'b1 | 1'b0 | Specifies whether or not to use the optional inversion on the PWRDWN pin. |
IS_RST_INVERTED | BINARY | 1'b0 to 1'b1 | 1'b0 | Specifies whether or not to use the optional inversion on the RST pin. |
REF_JITTER1 | 3 significant digit FLOAT | 0.000 to 0.999 | 0.010 | Specifies the expected jitter on the CLKIN1. |
REF_JITTER2 | 3 significant digit FLOAT | 0.000 to 0.999 | 0.010 | Specifies the expected jitter on the CLKIN2. |
SS_EN | STRING | "FALSE", "TRUE" | "FALSE" | Enables the spread spectrum feature for the MMCM. Used in conjunction with SS_MODE and SS_MOD_PERIOD attributes. |
SS_MOD_PERIOD | DECIMAL(nS) | 4000 to 40000 | 10000 | Specifies the spread spectrum modulation period (ns). |
SS_MODE | STRING | "CENTER_HIGH", "CENTER_LOW", "DOWN_HIGH", "DOWN_LOW" | "CENTER_HIGH" | Controls the spread spectrum frequency deviation and the spread type. |
STARTUP_WAIT | STRING | "FALSE", "TRUE" | "FALSE" | Delays configuration DONE signal from asserting until MMCM is locked. |
VHDL Instantiation Template
Unless they already exist, copy the following
two statements and paste them before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;
-- MMCME4_ADV: Advanced Mixed Mode Clock Manager (MMCM)
-- UltraScale
-- Xilinx HDL Language Template, version 2022.2
MMCME4_ADV_inst : MMCME4_ADV
generic map (
BANDWIDTH => "OPTIMIZED", -- Jitter programming
CLKFBOUT_MULT_F => 5.0, -- Multiply value for all CLKOUT
CLKFBOUT_PHASE => 0.0, -- Phase offset in degrees of CLKFB
CLKFBOUT_USE_FINE_PS => "FALSE", -- Fine phase shift enable (TRUE/FALSE)
CLKIN1_PERIOD => 0.0, -- Input clock period in ns to ps resolution (i.e., 33.333 is 30 MHz).
CLKIN2_PERIOD => 0.0, -- Input clock period in ns to ps resolution (i.e., 33.333 is 30 MHz).
CLKOUT0_DIVIDE_F => 1.0, -- Divide amount for CLKOUT0
CLKOUT0_DUTY_CYCLE => 0.5, -- Duty cycle for CLKOUT0
CLKOUT0_PHASE => 0.0, -- Phase offset for CLKOUT0
CLKOUT0_USE_FINE_PS => "FALSE", -- Fine phase shift enable (TRUE/FALSE)
CLKOUT1_DIVIDE => 1, -- Divide amount for CLKOUT (1-128)
CLKOUT1_DUTY_CYCLE => 0.5, -- Duty cycle for CLKOUT outputs (0.001-0.999).
CLKOUT1_PHASE => 0.0, -- Phase offset for CLKOUT outputs (-360.000-360.000).
CLKOUT1_USE_FINE_PS => "FALSE", -- Fine phase shift enable (TRUE/FALSE)
CLKOUT2_DIVIDE => 1, -- Divide amount for CLKOUT (1-128)
CLKOUT2_DUTY_CYCLE => 0.5, -- Duty cycle for CLKOUT outputs (0.001-0.999).
CLKOUT2_PHASE => 0.0, -- Phase offset for CLKOUT outputs (-360.000-360.000).
CLKOUT2_USE_FINE_PS => "FALSE", -- Fine phase shift enable (TRUE/FALSE)
CLKOUT3_DIVIDE => 1, -- Divide amount for CLKOUT (1-128)
CLKOUT3_DUTY_CYCLE => 0.5, -- Duty cycle for CLKOUT outputs (0.001-0.999).
CLKOUT3_PHASE => 0.0, -- Phase offset for CLKOUT outputs (-360.000-360.000).
CLKOUT3_USE_FINE_PS => "FALSE", -- Fine phase shift enable (TRUE/FALSE)
CLKOUT4_CASCADE => "FALSE", -- Divide amount for CLKOUT (1-128)
CLKOUT4_DIVIDE => 1, -- Divide amount for CLKOUT (1-128)
CLKOUT4_DUTY_CYCLE => 0.5, -- Duty cycle for CLKOUT outputs (0.001-0.999).
CLKOUT4_PHASE => 0.0, -- Phase offset for CLKOUT outputs (-360.000-360.000).
CLKOUT4_USE_FINE_PS => "FALSE", -- Fine phase shift enable (TRUE/FALSE)
CLKOUT5_DIVIDE => 1, -- Divide amount for CLKOUT (1-128)
CLKOUT5_DUTY_CYCLE => 0.5, -- Duty cycle for CLKOUT outputs (0.001-0.999).
CLKOUT5_PHASE => 0.0, -- Phase offset for CLKOUT outputs (-360.000-360.000).
CLKOUT5_USE_FINE_PS => "FALSE", -- Fine phase shift enable (TRUE/FALSE)
CLKOUT6_DIVIDE => 1, -- Divide amount for CLKOUT (1-128)
CLKOUT6_DUTY_CYCLE => 0.5, -- Duty cycle for CLKOUT outputs (0.001-0.999).
CLKOUT6_PHASE => 0.0, -- Phase offset for CLKOUT outputs (-360.000-360.000).
CLKOUT6_USE_FINE_PS => "FALSE", -- Fine phase shift enable (TRUE/FALSE)
COMPENSATION => "AUTO", -- Clock input compensation
DIVCLK_DIVIDE => 1, -- Master division value
IS_CLKFBIN_INVERTED => '0', -- Optional inversion for CLKFBIN
IS_CLKIN1_INVERTED => '0', -- Optional inversion for CLKIN1
IS_CLKIN2_INVERTED => '0', -- Optional inversion for CLKIN2
IS_CLKINSEL_INVERTED => '0', -- Optional inversion for CLKINSEL
IS_PSEN_INVERTED => '0', -- Optional inversion for PSEN
IS_PSINCDEC_INVERTED => '0', -- Optional inversion for PSINCDEC
IS_PWRDWN_INVERTED => '0', -- Optional inversion for PWRDWN
IS_RST_INVERTED => '0', -- Optional inversion for RST
REF_JITTER1 => 0.0, -- Reference input jitter in UI (0.000-0.999).
REF_JITTER2 => 0.0, -- Reference input jitter in UI (0.000-0.999).
SS_EN => "FALSE", -- Enables spread spectrum
SS_MODE => "CENTER_HIGH", -- Spread spectrum frequency deviation and the spread type
SS_MOD_PERIOD => 10000, -- Spread spectrum modulation period (ns)
STARTUP_WAIT => "FALSE" -- Delays DONE until MMCM is locked
)
port map (
CDDCDONE => CDDCDONE, -- 1-bit output: Clock dynamic divide done
CLKFBOUT => CLKFBOUT, -- 1-bit output: Feedback clock
CLKFBOUTB => CLKFBOUTB, -- 1-bit output: Inverted CLKFBOUT
CLKFBSTOPPED => CLKFBSTOPPED, -- 1-bit output: Feedback clock stopped
CLKINSTOPPED => CLKINSTOPPED, -- 1-bit output: Input clock stopped
CLKOUT0 => CLKOUT0, -- 1-bit output: CLKOUT0
CLKOUT0B => CLKOUT0B, -- 1-bit output: Inverted CLKOUT0
CLKOUT1 => CLKOUT1, -- 1-bit output: CLKOUT1
CLKOUT1B => CLKOUT1B, -- 1-bit output: Inverted CLKOUT1
CLKOUT2 => CLKOUT2, -- 1-bit output: CLKOUT2
CLKOUT2B => CLKOUT2B, -- 1-bit output: Inverted CLKOUT2
CLKOUT3 => CLKOUT3, -- 1-bit output: CLKOUT3
CLKOUT3B => CLKOUT3B, -- 1-bit output: Inverted CLKOUT3
CLKOUT4 => CLKOUT4, -- 1-bit output: CLKOUT4
CLKOUT5 => CLKOUT5, -- 1-bit output: CLKOUT5
CLKOUT6 => CLKOUT6, -- 1-bit output: CLKOUT6
DO => DO, -- 16-bit output: DRP data output
DRDY => DRDY, -- 1-bit output: DRP ready
LOCKED => LOCKED, -- 1-bit output: LOCK
PSDONE => PSDONE, -- 1-bit output: Phase shift done
CDDCREQ => CDDCREQ, -- 1-bit input: Request to dynamic divide clock
CLKFBIN => CLKFBIN, -- 1-bit input: Feedback clock
CLKIN1 => CLKIN1, -- 1-bit input: Primary clock
CLKIN2 => CLKIN2, -- 1-bit input: Secondary clock
CLKINSEL => CLKINSEL, -- 1-bit input: Clock select, High=CLKIN1 Low=CLKIN2
DADDR => DADDR, -- 7-bit input: DRP address
DCLK => DCLK, -- 1-bit input: DRP clock
DEN => DEN, -- 1-bit input: DRP enable
DI => DI, -- 16-bit input: DRP data input
DWE => DWE, -- 1-bit input: DRP write enable
PSCLK => PSCLK, -- 1-bit input: Phase shift clock
PSEN => PSEN, -- 1-bit input: Phase shift enable
PSINCDEC => PSINCDEC, -- 1-bit input: Phase shift increment/decrement
PWRDWN => PWRDWN, -- 1-bit input: Power-down
RST => RST -- 1-bit input: Reset
);
-- End of MMCME4_ADV_inst instantiation
Verilog Instantiation Template
// MMCME4_ADV: Advanced Mixed Mode Clock Manager (MMCM)
// UltraScale
// Xilinx HDL Language Template, version 2022.2
MMCME4_ADV #(
.BANDWIDTH("OPTIMIZED"), // Jitter programming
.CLKFBOUT_MULT_F(5.0), // Multiply value for all CLKOUT
.CLKFBOUT_PHASE(0.0), // Phase offset in degrees of CLKFB
.CLKFBOUT_USE_FINE_PS("FALSE"), // Fine phase shift enable (TRUE/FALSE)
.CLKIN1_PERIOD(0.0), // Input clock period in ns to ps resolution (i.e., 33.333 is 30 MHz).
.CLKIN2_PERIOD(0.0), // Input clock period in ns to ps resolution (i.e., 33.333 is 30 MHz).
.CLKOUT0_DIVIDE_F(1.0), // Divide amount for CLKOUT0
.CLKOUT0_DUTY_CYCLE(0.5), // Duty cycle for CLKOUT0
.CLKOUT0_PHASE(0.0), // Phase offset for CLKOUT0
.CLKOUT0_USE_FINE_PS("FALSE"), // Fine phase shift enable (TRUE/FALSE)
.CLKOUT1_DIVIDE(1), // Divide amount for CLKOUT (1-128)
.CLKOUT1_DUTY_CYCLE(0.5), // Duty cycle for CLKOUT outputs (0.001-0.999).
.CLKOUT1_PHASE(0.0), // Phase offset for CLKOUT outputs (-360.000-360.000).
.CLKOUT1_USE_FINE_PS("FALSE"), // Fine phase shift enable (TRUE/FALSE)
.CLKOUT2_DIVIDE(1), // Divide amount for CLKOUT (1-128)
.CLKOUT2_DUTY_CYCLE(0.5), // Duty cycle for CLKOUT outputs (0.001-0.999).
.CLKOUT2_PHASE(0.0), // Phase offset for CLKOUT outputs (-360.000-360.000).
.CLKOUT2_USE_FINE_PS("FALSE"), // Fine phase shift enable (TRUE/FALSE)
.CLKOUT3_DIVIDE(1), // Divide amount for CLKOUT (1-128)
.CLKOUT3_DUTY_CYCLE(0.5), // Duty cycle for CLKOUT outputs (0.001-0.999).
.CLKOUT3_PHASE(0.0), // Phase offset for CLKOUT outputs (-360.000-360.000).
.CLKOUT3_USE_FINE_PS("FALSE"), // Fine phase shift enable (TRUE/FALSE)
.CLKOUT4_CASCADE("FALSE"), // Divide amount for CLKOUT (1-128)
.CLKOUT4_DIVIDE(1), // Divide amount for CLKOUT (1-128)
.CLKOUT4_DUTY_CYCLE(0.5), // Duty cycle for CLKOUT outputs (0.001-0.999).
.CLKOUT4_PHASE(0.0), // Phase offset for CLKOUT outputs (-360.000-360.000).
.CLKOUT4_USE_FINE_PS("FALSE"), // Fine phase shift enable (TRUE/FALSE)
.CLKOUT5_DIVIDE(1), // Divide amount for CLKOUT (1-128)
.CLKOUT5_DUTY_CYCLE(0.5), // Duty cycle for CLKOUT outputs (0.001-0.999).
.CLKOUT5_PHASE(0.0), // Phase offset for CLKOUT outputs (-360.000-360.000).
.CLKOUT5_USE_FINE_PS("FALSE"), // Fine phase shift enable (TRUE/FALSE)
.CLKOUT6_DIVIDE(1), // Divide amount for CLKOUT (1-128)
.CLKOUT6_DUTY_CYCLE(0.5), // Duty cycle for CLKOUT outputs (0.001-0.999).
.CLKOUT6_PHASE(0.0), // Phase offset for CLKOUT outputs (-360.000-360.000).
.CLKOUT6_USE_FINE_PS("FALSE"), // Fine phase shift enable (TRUE/FALSE)
.COMPENSATION("AUTO"), // Clock input compensation
.DIVCLK_DIVIDE(1), // Master division value
.IS_CLKFBIN_INVERTED(1'b0), // Optional inversion for CLKFBIN
.IS_CLKIN1_INVERTED(1'b0), // Optional inversion for CLKIN1
.IS_CLKIN2_INVERTED(1'b0), // Optional inversion for CLKIN2
.IS_CLKINSEL_INVERTED(1'b0), // Optional inversion for CLKINSEL
.IS_PSEN_INVERTED(1'b0), // Optional inversion for PSEN
.IS_PSINCDEC_INVERTED(1'b0), // Optional inversion for PSINCDEC
.IS_PWRDWN_INVERTED(1'b0), // Optional inversion for PWRDWN
.IS_RST_INVERTED(1'b0), // Optional inversion for RST
.REF_JITTER1(0.0), // Reference input jitter in UI (0.000-0.999).
.REF_JITTER2(0.0), // Reference input jitter in UI (0.000-0.999).
.SS_EN("FALSE"), // Enables spread spectrum
.SS_MODE("CENTER_HIGH"), // Spread spectrum frequency deviation and the spread type
.SS_MOD_PERIOD(10000), // Spread spectrum modulation period (ns)
.STARTUP_WAIT("FALSE") // Delays DONE until MMCM is locked
)
MMCME4_ADV_inst (
.CDDCDONE(CDDCDONE), // 1-bit output: Clock dynamic divide done
.CLKFBOUT(CLKFBOUT), // 1-bit output: Feedback clock
.CLKFBOUTB(CLKFBOUTB), // 1-bit output: Inverted CLKFBOUT
.CLKFBSTOPPED(CLKFBSTOPPED), // 1-bit output: Feedback clock stopped
.CLKINSTOPPED(CLKINSTOPPED), // 1-bit output: Input clock stopped
.CLKOUT0(CLKOUT0), // 1-bit output: CLKOUT0
.CLKOUT0B(CLKOUT0B), // 1-bit output: Inverted CLKOUT0
.CLKOUT1(CLKOUT1), // 1-bit output: CLKOUT1
.CLKOUT1B(CLKOUT1B), // 1-bit output: Inverted CLKOUT1
.CLKOUT2(CLKOUT2), // 1-bit output: CLKOUT2
.CLKOUT2B(CLKOUT2B), // 1-bit output: Inverted CLKOUT2
.CLKOUT3(CLKOUT3), // 1-bit output: CLKOUT3
.CLKOUT3B(CLKOUT3B), // 1-bit output: Inverted CLKOUT3
.CLKOUT4(CLKOUT4), // 1-bit output: CLKOUT4
.CLKOUT5(CLKOUT5), // 1-bit output: CLKOUT5
.CLKOUT6(CLKOUT6), // 1-bit output: CLKOUT6
.DO(DO), // 16-bit output: DRP data output
.DRDY(DRDY), // 1-bit output: DRP ready
.LOCKED(LOCKED), // 1-bit output: LOCK
.PSDONE(PSDONE), // 1-bit output: Phase shift done
.CDDCREQ(CDDCREQ), // 1-bit input: Request to dynamic divide clock
.CLKFBIN(CLKFBIN), // 1-bit input: Feedback clock
.CLKIN1(CLKIN1), // 1-bit input: Primary clock
.CLKIN2(CLKIN2), // 1-bit input: Secondary clock
.CLKINSEL(CLKINSEL), // 1-bit input: Clock select, High=CLKIN1 Low=CLKIN2
.DADDR(DADDR), // 7-bit input: DRP address
.DCLK(DCLK), // 1-bit input: DRP clock
.DEN(DEN), // 1-bit input: DRP enable
.DI(DI), // 16-bit input: DRP data input
.DWE(DWE), // 1-bit input: DRP write enable
.PSCLK(PSCLK), // 1-bit input: Phase shift clock
.PSEN(PSEN), // 1-bit input: Phase shift enable
.PSINCDEC(PSINCDEC), // 1-bit input: Phase shift increment/decrement
.PWRDWN(PWRDWN), // 1-bit input: Power-down
.RST(RST) // 1-bit input: Reset
);
// End of MMCME4_ADV_inst instantiation
Related Information
- See the UltraScale Architecture Clocking Resources User Guide (UG572).