Primitive: Advanced Mixed Mode Clock Manager (MMCM)
- PRIMITIVE_GROUP: CLOCK
- PRIMITIVE_SUBGROUP: PLL
- Families: UltraScale, UltraScale+
Introduction
The MMCME3 is a mixed signal block designed to support frequency synthesis, clock network deskew, and jitter reduction. The clock outputs can each have an individual divide, phase shift, and duty cycle based on the same VCO frequency. The MMCME3 also supports dynamic phase shifting and fractional divides.
Port Descriptions
Port | Direction | Width | Function |
---|---|---|---|
CDDCREQ | Input | 1 | Active-High request signal for dynamically changing output clock divide. |
Clock Inputs: MMCM input clock(s). Connect CLKIN2 if input clock multiplexing feature is used. | |||
CLKIN1 | Input | 1 | Primary clock input. |
CLKIN2 | Input | 1 | Secondary clock input to dynamically switch the MMCM reference clock. |
Clock Outputs: User configurable clock outputs that can be divided versions of the VCO phase outputs (user controllable) from 1 (bypassed) to 128. The output clocks are phase aligned to each other (unless phase shifted) and aligned to the input clock with a proper feedback configuration. The CLKOUT#B outputs are 180 degrees out of phase with the non-B outputs. | |||
CLKOUT0 | Output | 1 | CLKOUT0 output. |
CLKOUT0B | Output | 1 | User configurable clock outputs that can be divided versions of the VCO phase outputs (user controllable) from 1 (bypassed) to 128. The output clocks are phase aligned to each other (unless phase shifted) and aligned to the input clock with a proper feedback configuration. The CLKOUT#B outputs are 180 degrees out of phase with the non-B outputs. |
CLKOUT1 | Output | 1 | CLKOUT1 output. |
CLKOUT1B | Output | 1 | Inverted CLKOUT1 output. |
CLKOUT2 | Output | 1 | User configurable clock outputs that can be divided versions of the VCO phase outputs (user controllable) from 1 (bypassed) to 128. The output clocks are phase aligned to each other (unless phase shifted) and aligned to the input clock with a proper feedback configuration. The CLKOUT#B outputs are 180 degrees out of phase with the non-B outputs. |
CLKOUT2B | Output | 1 | Inverted CLKOUT2 output. |
CLKOUT3 | Output | 1 | CLKOUT3 output. |
CLKOUT3B | Output | 1 | Inverted CLKOUT3 output. |
CLKOUT4 | Output | 1 | CLKOUT4 output. |
CLKOUT5 | Output | 1 | CLKOUT5 output. |
CLKOUT6 | Output | 1 | CLKOUT6 output. |
Control Ports: MMCM control ports. | |||
CLKINSEL | Input | 1 | Signal controls the state of the input MUX, High = CLKIN1, Low = CLKIN2. |
PWRDWN | Input | 1 | Powers down MMCM components, thus reducing power consumption when derived clocks are not in use for sustained periods of time. Upon release of PWRDWN, the MMCM must regain LOCK before use. |
RST | Input | 1 | Asynchronous reset signal. The MMCM will synchronously re-enable itself when this signal is released (i.e., MMCM re-enabled). A reset is required when the input clock conditions change (for example, frequency). |
DRP Ports: Ports used when using the dynamic reconfigurable ports for reading and writing the configuration of the MMCM. | |||
DADDR<6:0> | Input | 7 | The dynamic reconfiguration address (DADDR) input bus provides a reconfiguration address for the dynamic reconfiguration. When not used, all bits must be assigned zeros. |
DCLK | Input | 1 | The DCLK signal is the reference clock for the dynamic reconfiguration port. |
DEN | Input | 1 | The dynamic reconfiguration enable (DEN) provides the enable control signal to access the dynamic reconfiguration feature. When the dynamic reconfiguration feature is not used, DEN must be tied Low. |
DI<15:0> | Input | 16 | The dynamic reconfiguration data input (DI) bus provides reconfiguration data. When not used, all bits must be set to zero. |
DO<15:0> | Output | 16 | The dynamic reconfiguration output bus provides MMCM data output when using dynamic reconfiguration. |
DRDY | Output | 1 | The dynamic reconfiguration ready output (DRDY) provides the response to the DEN signal for the MMCMs dynamic reconfiguration feature. |
DWE | Input | 1 | The dynamic reconfiguration write enable (DWE) input pin provides the write enable control signal to write the DI data into the DADDR address. When not used, it must be tied Low. |
Dynamic Phase Shift Ports: Ports used when using the dynamic phase shift capability of the MMCM. | |||
PSCLK | Input | 1 | Phase shift clock. |
PSDONE | Output | 1 | Phase shift done. |
PSEN | Input | 1 | Phase shift enable. |
PSINCDEC | Input | 1 | Phase shift increment/decrement control. |
Feedback: Required ports to form the feedback path for the MMCM phase alignment capabilities. | |||
CLKFBIN | Input | 1 | Feedback clock pin to the MMCM. |
CLKFBOUT | Output | 1 | Dedicated MMCM Feedback clock output. |
CLKFBOUTB | Output | 1 | Inverted CLKFBOUT. |
Status Ports: MMCM status ports. | |||
CDDCDONE | Output | 1 | Acknowledge signal that output clock dynamic divide is done and the output is valid. |
CLKFBSTOPPED | Output | 1 | Status pin indicating that the feedback clock has stopped. |
CLKINSTOPPED | Output | 1 | Status pin indicating that the input clock has stopped. |
LOCKED | Output | 1 | An output from the MMCM that indicates when the MMCM has achieved phase alignment within a predefined window and frequency matching within a predefined PPM range. The MMCM automatically locks after power on, no extra reset is required. LOCKED will be deasserted if the input clock stops or the phase alignment is violated (for example, input clock phase shift). The MMCM must be reset after LOCKED is deasserted. |
Design Entry Method
Instantiation | Yes |
Inference | No |
IP and IP Integrator Catalog | Recommended |
Available Attributes
Attribute | Type | Allowed Values | Default | Description |
---|---|---|---|---|
BANDWIDTH | STRING | "OPTIMIZED", "HIGH", "LOW" | "OPTIMIZED" | Specifies the MMCM programming algorithm affecting the jitter, phase margin and other characteristics of the MMCM. |
CLKFBOUT_MULT_F | 3 significant digit FLOAT | 2.000 to 64.000 | 5.000 | Specifies the amount to multiply all CLKOUT clock outputs if a different frequency is desired. This number, in combination with the associated CLKOUT#_DIVIDE value and DIVCLK_DIVIDE value, will determine the output frequency. |
CLKFBOUT_PHASE | 3 significant digit FLOAT | -360.000 to 360.000 | 0.000 | Specifies the phase offset in degrees of the clock feedback output. Shifting the feedback clock results in a negative phase shift of all output clocks to the MMCM. |
CLKOUT0_DIVIDE_F | 3 significant digit FLOAT | 1.000 to 128.000 | 1.000 | Specifies the amount to fractional divide the associated CLKOUT clock output if a different frequency is desired. This number in combination with the CLKFBOUT_MULT_F and DIVCLK_DIVIDE values will determine the output frequency. |
COMPENSATION | STRING | "AUTO", "BUF_IN", "EXTERNAL", "INTERNAL", "ZHOLD" | "AUTO" | Clock input compensation. Should be set to AUTO. Defines how the MMCM feedback is configured.
|
DIVCLK_DIVIDE | DECIMAL | 1 to 106 | 1 | Specifies the division ratio for all output clocks with respect to the input clock. Effectively divides the CLKIN going into the PFD. |
STARTUP_WAIT | STRING | "FALSE", "TRUE" | "FALSE" | Delays configuration DONE signal from asserting until MMCM is locked. |
CLKIN_PERIOD: Specifies the input period in ns to the MMCM CLKIN inputs. Resolution is down to the ps. For example, a value of 33.333 would indicate a 30 MHz input clock. This information is mandatory and must be supplied. CLKIN1_PERIOD relates to the input period on the CLKIN1 input, while CLKIN2_PERIOD relates to the input clock period on the CLKIN2 input. | ||||
CLKIN1_PERIOD | FLOAT(nS) | 0.000 to 100.000 | 0.000 | Specifies the input period to the CLKIN1 in ns. |
CLKIN2_PERIOD | FLOAT(nS) | 0.000 to 100.000 | 0.000 | Specifies the input period to the CLKIN2 in ns. |
CLKOUT0_DUTY_CYCLE - CLKOUT6_DUTY_CYCLE: Specifies the duty cycle of the associated CLKOUT output as a decimal number representing the percentage (i.e., 0.50 will generate a 50% duty cycle). | ||||
CLKOUT0_DUTY_CYCLE | 3 significant digit FLOAT | 0.001 to 0.999 | 0.500 | Specifies the duty cycle for CLKOUT0. |
CLKOUT1_DUTY_CYCLE | 3 significant digit FLOAT | 0.001 to 0.999 | 0.500 | Specifies the duty cycle for CLKOUT1. |
CLKOUT2_DUTY_CYCLE | 3 significant digit FLOAT | 0.001 to 0.999 | 0.500 | Specifies the duty cycle for CLKOUT2. |
CLKOUT3_DUTY_CYCLE | 3 significant digit FLOAT | 0.001 to 0.999 | 0.500 | Specifies the duty cycle for CLKOUT3. |
CLKOUT4_DUTY_CYCLE | 3 significant digit FLOAT | 0.001 to 0.999 | 0.500 | Specifies the duty cycle for CLKOUT4. |
CLKOUT5_DUTY_CYCLE | 3 significant digit FLOAT | 0.001 to 0.999 | 0.500 | Specifies the duty cycle for CLKOUT5. |
CLKOUT6_DUTY_CYCLE | 3 significant digit FLOAT | 0.001 to 0.999 | 0.500 | Specifies the duty cycle for CLKOUT6. |
CLKOUT0_PHASE - CLKOUT6_PHASE: Specifies the phase offset in degrees of the clock feedback output. Shifting the feedback clock results in a negative phase shift of all output clocks to the MMCM. | ||||
CLKOUT0_PHASE | 3 significant digit FLOAT | -360.000 to 360.000 | 0.000 | Specifies the phase offset for CLKOUT0. |
CLKOUT1_PHASE | 3 significant digit FLOAT | -360.000 to 360.000 | 0.000 | Specifies the phase offset for CLKOUT1. |
CLKOUT2_PHASE | 3 significant digit FLOAT | -360.000 to 360.000 | 0.000 | Specifies the phase offset for CLKOUT2. |
CLKOUT3_PHASE | 3 significant digit FLOAT | -360.000 to 360.000 | 0.000 | Specifies the phase offset for CLKOUT3. |
CLKOUT4_PHASE | 3 significant digit FLOAT | -360.000 to 360.000 | 0.000 | Specifies the phase offset for CLKOUT4. |
CLKOUT5_PHASE | 3 significant digit FLOAT | -360.000 to 360.000 | 0.000 | Specifies the phase offset for CLKOUT5. |
CLKOUT6_PHASE | 3 significant digit FLOAT | -360.000 to 360.000 | 0.000 | Specifies the phase offset for CLKOUT6. |
CLKOUT1_DIVIDE - CLKOUT6_DIVIDE: Specifies the amount to divide the associated CLKOUT clock output if a different frequency is desired. This number in combination with the CLKFBOUT_MULT_F and DIVCLK_DIVIDE values will determine the output frequency. | ||||
CLKOUT1_DIVIDE | DECIMAL | 1 to 128 | 1 | Specifies the amount by which to divide CLKOUT1 to create a different frequency. |
CLKOUT2_DIVIDE | DECIMAL | 1 to 128 | 1 | Specifies the amount by which to divide CLKOUT2 to create a different frequency. |
CLKOUT3_DIVIDE | DECIMAL | 1 to 128 | 1 | Specifies the amount by which to divide CLKOUT3 to create a different frequency. |
CLKOUT4_CASCADE | STRING | "FALSE", "TRUE" | "FALSE" | Cascades the output divider (counter) CLKOUT6 into the input of the CLKOUT4 divider for an output clock divider that is greater than 128, effectively providing a total divide value of 16,384. |
CLKOUT4_DIVIDE | DECIMAL | 1 to 128 | 1 | Specifies the amount by which to divide CLKOUT4 to create a different frequency. |
CLKOUT5_DIVIDE | DECIMAL | 1 to 128 | 1 | Specifies the amount by which to divide CLKOUT5 to create a different frequency. |
CLKOUT6_DIVIDE | DECIMAL | 1 to 128 | 1 | Specifies the amount by which to divide CLKOUT6 to create a different frequency. |
Programmable Inversion Attributes: Specifies whether or not to use the optional inversions on specific pins for this component to change the active polarity of the pin function. When set to 1 on a clock input pin (CLKIN# or CLKFBIN), the phase is effectively shifted 180 degrees. When set to 1 on other pins, it changes the function to behave active-Low rather than active-High. If an external inverter is specified on one of these associated pins, the Vivado Design Suite will automatically set this attribute during the opt_design stage so that additional logic is not necessary for changing the input polarity. | ||||
IS_CLKFBIN_INVERTED | BINARY | 1'b0 to 1'b1 | 1'b0 | Specifies whether or not to use the optional inversion on the CLKFBIN pin. |
IS_CLKINSEL_INVERTED | BINARY | 1'b0 to 1'b1 | 1'b0 | Specifies whether or not to use the optional inversion on the CLKINSEL pin. |
IS_CLKIN1_INVERTED | BINARY | 1'b0 to 1'b1 | 1'b0 | Specifies whether or not to use the optional inversion on the CLKIN1 pin. |
IS_CLKIN2_INVERTED | BINARY | 1'b0 to 1'b1 | 1'b0 | Specifies whether or not to use the optional inversion on the CLKIN2 pin. |
IS_PSEN_INVERTED | BINARY | 1'b0 to 1'b1 | 1'b0 | Specifies whether or not to use the optional inversion on the PSEN pin. |
IS_PSINCDEC_INVERTED | BINARY | 1'b0 to 1'b1 | 1'b0 | Specifies whether or not to use the optional inversion on the PSINCDEC pin. |
IS_PWRDWN_INVERTED | BINARY | 1'b0 to 1'b1 | 1'b0 | Specifies whether or not to use the optional inversion on the PWRDWN pin. |
IS_RST_INVERTED | BINARY | 1'b0 to 1'b1 | 1'b0 | Specifies whether or not to use the optional inversion on the RST pin. |
REF_JITTER: Specifies the expected jitter on the CLKIN inputs to better optimize MMCM performance. A bandwidth setting of OPTIMIZED will attempt to choose the best parameter for input clocking when unknown. If known, then the value provided should be specified in terms of the UI percentage (the maximum peak to peak value) of the expected jitter on the input clock. | ||||
REF_JITTER1 | 3 significant digit FLOAT | 0.000 to 0.999 | 0.010 | Specifies the expected jitter on the CLKIN1. |
REF_JITTER2 | 3 significant digit FLOAT | 0.000 to 0.999 | 0.010 | Specifies the expected jitter on the CLKIN2. |
Spread Spectrum: Spread Spectrum Attributes. | ||||
SS_EN | STRING | "FALSE", "TRUE" | "FALSE" | Enables the spread spectrum feature for the MMCM. Used in conjunction with SS_MODE and SS_MOD_PERIOD attributes. |
SS_MOD_PERIOD | DECIMAL(nS) | 4000 to 40000 | 10000 | Specifies the spread spectrum modulation period (ns). |
SS_MODE | STRING | "CENTER_HIGH", "CENTER_LOW", "DOWN_HIGH", "DOWN_LOW" | "CENTER_HIGH" | Controls the spread spectrum frequency deviation and the spread type. |
USE_FINE_PS: Counter variable fine phase shift enable. | ||||
CLKFBOUT_USE_FINE_PS | STRING | "FALSE", "TRUE" | "FALSE" | Counter variable fine phase shift enable. |
CLKOUT0_USE_FINE_PS | STRING | "FALSE", "TRUE" | "FALSE" | Counter variable fine phase shift enable. |
CLKOUT1_USE_FINE_PS | STRING | "FALSE", "TRUE" | "FALSE" | Counter variable fine phase shift enable. |
CLKOUT2_USE_FINE_PS | STRING | "FALSE", "TRUE" | "FALSE" | Counter variable fine phase shift enable. |
CLKOUT3_USE_FINE_PS | STRING | "FALSE", "TRUE" | "FALSE" | Counter variable fine phase shift enable. |
CLKOUT4_USE_FINE_PS | STRING | "FALSE", "TRUE" | "FALSE" | Counter variable fine phase shift enable. |
CLKOUT5_USE_FINE_PS | STRING | "FALSE", "TRUE" | "FALSE" | Counter variable fine phase shift enable. |
CLKOUT6_USE_FINE_PS | STRING | "FALSE", "TRUE" | "FALSE" | Counter variable fine phase shift enable. |
VHDL Instantiation Template
Unless they already exist, copy the following
two statements and paste them before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;
-- MMCME3_ADV: Advanced Mixed Mode Clock Manager (MMCM)
-- UltraScale
-- Xilinx HDL Language Template, version 2022.2
MMCME3_ADV_inst : MMCME3_ADV
generic map (
BANDWIDTH => "OPTIMIZED", -- Jitter programming (HIGH, LOW, OPTIMIZED)
CLKFBOUT_MULT_F => 5.0, -- Multiply value for all CLKOUT (2.000-64.000)
CLKFBOUT_PHASE => 0.0, -- Phase offset in degrees of CLKFB (-360.000-360.000)
-- CLKIN_PERIOD: Input clock period in ns units, ps resolution (i.e., 33.333 is 30 MHz).
CLKIN1_PERIOD => 0.0,
CLKIN2_PERIOD => 0.0,
CLKOUT0_DIVIDE_F => 1.0, -- Divide amount for CLKOUT0 (1.000-128.000)
-- CLKOUT0_DUTY_CYCLE - CLKOUT6_DUTY_CYCLE: Duty cycle for CLKOUT outputs (0.001-0.999).
CLKOUT0_DUTY_CYCLE => 0.5,
CLKOUT1_DUTY_CYCLE => 0.5,
CLKOUT2_DUTY_CYCLE => 0.5,
CLKOUT3_DUTY_CYCLE => 0.5,
CLKOUT4_DUTY_CYCLE => 0.5,
CLKOUT5_DUTY_CYCLE => 0.5,
CLKOUT6_DUTY_CYCLE => 0.5,
-- CLKOUT0_PHASE - CLKOUT6_PHASE: Phase offset for CLKOUT outputs (-360.000-360.000).
CLKOUT0_PHASE => 0.0,
CLKOUT1_PHASE => 0.0,
CLKOUT2_PHASE => 0.0,
CLKOUT3_PHASE => 0.0,
CLKOUT4_PHASE => 0.0,
CLKOUT5_PHASE => 0.0,
CLKOUT6_PHASE => 0.0,
-- CLKOUT1_DIVIDE - CLKOUT6_DIVIDE: Divide amount for CLKOUT (1-128)
CLKOUT1_DIVIDE => 1,
CLKOUT2_DIVIDE => 1,
CLKOUT3_DIVIDE => 1,
CLKOUT4_CASCADE => "FALSE",
CLKOUT4_DIVIDE => 1,
CLKOUT5_DIVIDE => 1,
CLKOUT6_DIVIDE => 1,
COMPENSATION => "AUTO", -- AUTO, BUF_IN, EXTERNAL, INTERNAL, ZHOLD
DIVCLK_DIVIDE => 1, -- Master division value (1-106)
-- Programmable Inversion Attributes: Specifies built-in programmable inversion on specific pins
IS_CLKFBIN_INVERTED => '0', -- Optional inversion for CLKFBIN
IS_CLKIN1_INVERTED => '0', -- Optional inversion for CLKIN1
IS_CLKIN2_INVERTED => '0', -- Optional inversion for CLKIN2
IS_CLKINSEL_INVERTED => '0', -- Optional inversion for CLKINSEL
IS_PSEN_INVERTED => '0', -- Optional inversion for PSEN
IS_PSINCDEC_INVERTED => '0', -- Optional inversion for PSINCDEC
IS_PWRDWN_INVERTED => '0', -- Optional inversion for PWRDWN
IS_RST_INVERTED => '0', -- Optional inversion for RST
-- REF_JITTER: Reference input jitter in UI (0.000-0.999).
REF_JITTER1 => 0.0,
REF_JITTER2 => 0.0,
STARTUP_WAIT => "FALSE", -- Delays DONE until MMCM is locked (FALSE, TRUE)
-- Spread Spectrum: Spread Spectrum Attributes.
SS_EN => "FALSE", -- Enables spread spectrum (FALSE, TRUE)
SS_MODE => "CENTER_HIGH", -- CENTER_HIGH, CENTER_LOW, DOWN_HIGH, DOWN_LOW
SS_MOD_PERIOD => 10000, -- Spread spectrum modulation period (ns) (4000-40000)
-- USE_FINE_PS: Fine phase shift enable (TRUE/FALSE)
CLKFBOUT_USE_FINE_PS => "FALSE",
CLKOUT0_USE_FINE_PS => "FALSE",
CLKOUT1_USE_FINE_PS => "FALSE",
CLKOUT2_USE_FINE_PS => "FALSE",
CLKOUT3_USE_FINE_PS => "FALSE",
CLKOUT4_USE_FINE_PS => "FALSE",
CLKOUT5_USE_FINE_PS => "FALSE",
CLKOUT6_USE_FINE_PS => "FALSE"
)
port map (
-- Clock Outputs outputs: User configurable clock outputs
CLKOUT0 => CLKOUT0, -- 1-bit output: CLKOUT0
CLKOUT0B => CLKOUT0B, -- 1-bit output: Inverted CLKOUT0.
CLKOUT1 => CLKOUT1, -- 1-bit output: Primary clock
CLKOUT1B => CLKOUT1B, -- 1-bit output: Inverted CLKOUT1
CLKOUT2 => CLKOUT2, -- 1-bit output: CLKOUT2
CLKOUT2B => CLKOUT2B, -- 1-bit output: Inverted CLKOUT2
CLKOUT3 => CLKOUT3, -- 1-bit output: CLKOUT3
CLKOUT3B => CLKOUT3B, -- 1-bit output: Inverted CLKOUT3
CLKOUT4 => CLKOUT4, -- 1-bit output: CLKOUT4
CLKOUT5 => CLKOUT5, -- 1-bit output: CLKOUT5
CLKOUT6 => CLKOUT6, -- 1-bit output: CLKOUT6
-- DRP Ports outputs: Dynamic reconfiguration ports
DO => DO, -- 16-bit output: DRP data
DRDY => DRDY, -- 1-bit output: DRP ready
-- Dynamic Phase Shift Ports outputs: Ports used for dynamic phase shifting of the outputs
PSDONE => PSDONE, -- 1-bit output: Phase shift done
-- Feedback outputs: Clock feedback ports
CLKFBOUT => CLKFBOUT, -- 1-bit output: Feedback clock
CLKFBOUTB => CLKFBOUTB, -- 1-bit output: Inverted CLKFBOUT
-- Status Ports outputs: MMCM status ports
CDDCDONE => CDDCDONE, -- 1-bit output: Clock dynamic divide done
CLKFBSTOPPED => CLKFBSTOPPED, -- 1-bit output: Feedback clock stopped
CLKINSTOPPED => CLKINSTOPPED, -- 1-bit output: Input clock stopped
LOCKED => LOCKED, -- 1-bit output: LOCK
CDDCREQ => CDDCREQ, -- 1-bit input: Request to dynamic divide clock
-- Clock Inputs inputs: Clock inputs
CLKIN1 => CLKIN1, -- 1-bit input: Primary clock
CLKIN2 => CLKIN2, -- 1-bit input: Secondary clock
-- Control Ports inputs: MMCM control ports
CLKINSEL => CLKINSEL, -- 1-bit input: Clock select, High=CLKIN1 Low=CLKIN2
PWRDWN => PWRDWN, -- 1-bit input: Power-down
RST => RST, -- 1-bit input: Reset
-- DRP Ports inputs: Dynamic reconfiguration ports
DADDR => DADDR, -- 7-bit input: DRP address
DCLK => DCLK, -- 1-bit input: DRP clock
DEN => DEN, -- 1-bit input: DRP enable
DI => DI, -- 16-bit input: DRP data
DWE => DWE, -- 1-bit input: DRP write enable
-- Dynamic Phase Shift Ports inputs: Ports used for dynamic phase shifting of the outputs
PSCLK => PSCLK, -- 1-bit input: Phase shift clock
PSEN => PSEN, -- 1-bit input: Phase shift enable
PSINCDEC => PSINCDEC, -- 1-bit input: Phase shift increment/decrement
-- Feedback inputs: Clock feedback ports
CLKFBIN => CLKFBIN -- 1-bit input: Feedback clock
);
-- End of MMCME3_ADV_inst instantiation
Verilog Instantiation Template
// MMCME3_ADV: Advanced Mixed Mode Clock Manager (MMCM)
// UltraScale
// Xilinx HDL Language Template, version 2022.2
MMCME3_ADV #(
.BANDWIDTH("OPTIMIZED"), // Jitter programming (HIGH, LOW, OPTIMIZED)
.CLKFBOUT_MULT_F(5.0), // Multiply value for all CLKOUT (2.000-64.000)
.CLKFBOUT_PHASE(0.0), // Phase offset in degrees of CLKFB (-360.000-360.000)
// CLKIN_PERIOD: Input clock period in ns units, ps resolution (i.e., 33.333 is 30 MHz).
.CLKIN1_PERIOD(0.0),
.CLKIN2_PERIOD(0.0),
.CLKOUT0_DIVIDE_F(1.0), // Divide amount for CLKOUT0 (1.000-128.000)
// CLKOUT0_DUTY_CYCLE - CLKOUT6_DUTY_CYCLE: Duty cycle for CLKOUT outputs (0.001-0.999).
.CLKOUT0_DUTY_CYCLE(0.5),
.CLKOUT1_DUTY_CYCLE(0.5),
.CLKOUT2_DUTY_CYCLE(0.5),
.CLKOUT3_DUTY_CYCLE(0.5),
.CLKOUT4_DUTY_CYCLE(0.5),
.CLKOUT5_DUTY_CYCLE(0.5),
.CLKOUT6_DUTY_CYCLE(0.5),
// CLKOUT0_PHASE - CLKOUT6_PHASE: Phase offset for CLKOUT outputs (-360.000-360.000).
.CLKOUT0_PHASE(0.0),
.CLKOUT1_PHASE(0.0),
.CLKOUT2_PHASE(0.0),
.CLKOUT3_PHASE(0.0),
.CLKOUT4_PHASE(0.0),
.CLKOUT5_PHASE(0.0),
.CLKOUT6_PHASE(0.0),
// CLKOUT1_DIVIDE - CLKOUT6_DIVIDE: Divide amount for CLKOUT (1-128)
.CLKOUT1_DIVIDE(1),
.CLKOUT2_DIVIDE(1),
.CLKOUT3_DIVIDE(1),
.CLKOUT4_CASCADE("FALSE"),
.CLKOUT4_DIVIDE(1),
.CLKOUT5_DIVIDE(1),
.CLKOUT6_DIVIDE(1),
.COMPENSATION("AUTO"), // AUTO, BUF_IN, EXTERNAL, INTERNAL, ZHOLD
.DIVCLK_DIVIDE(1), // Master division value (1-106)
// Programmable Inversion Attributes: Specifies built-in programmable inversion on specific pins
.IS_CLKFBIN_INVERTED(1'b0), // Optional inversion for CLKFBIN
.IS_CLKIN1_INVERTED(1'b0), // Optional inversion for CLKIN1
.IS_CLKIN2_INVERTED(1'b0), // Optional inversion for CLKIN2
.IS_CLKINSEL_INVERTED(1'b0), // Optional inversion for CLKINSEL
.IS_PSEN_INVERTED(1'b0), // Optional inversion for PSEN
.IS_PSINCDEC_INVERTED(1'b0), // Optional inversion for PSINCDEC
.IS_PWRDWN_INVERTED(1'b0), // Optional inversion for PWRDWN
.IS_RST_INVERTED(1'b0), // Optional inversion for RST
// REF_JITTER: Reference input jitter in UI (0.000-0.999).
.REF_JITTER1(0.0),
.REF_JITTER2(0.0),
.STARTUP_WAIT("FALSE"), // Delays DONE until MMCM is locked (FALSE, TRUE)
// Spread Spectrum: Spread Spectrum Attributes.
.SS_EN("FALSE"), // Enables spread spectrum (FALSE, TRUE)
.SS_MODE("CENTER_HIGH"), // CENTER_HIGH, CENTER_LOW, DOWN_HIGH, DOWN_LOW
.SS_MOD_PERIOD(10000), // Spread spectrum modulation period (ns) (4000-40000)
// USE_FINE_PS: Fine phase shift enable (TRUE/FALSE)
.CLKFBOUT_USE_FINE_PS("FALSE"),
.CLKOUT0_USE_FINE_PS("FALSE"),
.CLKOUT1_USE_FINE_PS("FALSE"),
.CLKOUT2_USE_FINE_PS("FALSE"),
.CLKOUT3_USE_FINE_PS("FALSE"),
.CLKOUT4_USE_FINE_PS("FALSE"),
.CLKOUT5_USE_FINE_PS("FALSE"),
.CLKOUT6_USE_FINE_PS("FALSE")
)
MMCME3_ADV_inst (
// Clock Outputs outputs: User configurable clock outputs
.CLKOUT0(CLKOUT0), // 1-bit output: CLKOUT0
.CLKOUT0B(CLKOUT0B), // 1-bit output: Inverted CLKOUT0.
.CLKOUT1(CLKOUT1), // 1-bit output: Primary clock
.CLKOUT1B(CLKOUT1B), // 1-bit output: Inverted CLKOUT1
.CLKOUT2(CLKOUT2), // 1-bit output: CLKOUT2
.CLKOUT2B(CLKOUT2B), // 1-bit output: Inverted CLKOUT2
.CLKOUT3(CLKOUT3), // 1-bit output: CLKOUT3
.CLKOUT3B(CLKOUT3B), // 1-bit output: Inverted CLKOUT3
.CLKOUT4(CLKOUT4), // 1-bit output: CLKOUT4
.CLKOUT5(CLKOUT5), // 1-bit output: CLKOUT5
.CLKOUT6(CLKOUT6), // 1-bit output: CLKOUT6
// DRP Ports outputs: Dynamic reconfiguration ports
.DO(DO), // 16-bit output: DRP data
.DRDY(DRDY), // 1-bit output: DRP ready
// Dynamic Phase Shift Ports outputs: Ports used for dynamic phase shifting of the outputs
.PSDONE(PSDONE), // 1-bit output: Phase shift done
// Feedback outputs: Clock feedback ports
.CLKFBOUT(CLKFBOUT), // 1-bit output: Feedback clock
.CLKFBOUTB(CLKFBOUTB), // 1-bit output: Inverted CLKFBOUT
// Status Ports outputs: MMCM status ports
.CDDCDONE(CDDCDONE), // 1-bit output: Clock dynamic divide done
.CLKFBSTOPPED(CLKFBSTOPPED), // 1-bit output: Feedback clock stopped
.CLKINSTOPPED(CLKINSTOPPED), // 1-bit output: Input clock stopped
.LOCKED(LOCKED), // 1-bit output: LOCK
.CDDCREQ(CDDCREQ), // 1-bit input: Request to dynamic divide clock
// Clock Inputs inputs: Clock inputs
.CLKIN1(CLKIN1), // 1-bit input: Primary clock
.CLKIN2(CLKIN2), // 1-bit input: Secondary clock
// Control Ports inputs: MMCM control ports
.CLKINSEL(CLKINSEL), // 1-bit input: Clock select, High=CLKIN1 Low=CLKIN2
.PWRDWN(PWRDWN), // 1-bit input: Power-down
.RST(RST), // 1-bit input: Reset
// DRP Ports inputs: Dynamic reconfiguration ports
.DADDR(DADDR), // 7-bit input: DRP address
.DCLK(DCLK), // 1-bit input: DRP clock
.DEN(DEN), // 1-bit input: DRP enable
.DI(DI), // 16-bit input: DRP data
.DWE(DWE), // 1-bit input: DRP write enable
// Dynamic Phase Shift Ports inputs: Ports used for dynamic phase shifting of the outputs
.PSCLK(PSCLK), // 1-bit input: Phase shift clock
.PSEN(PSEN), // 1-bit input: Phase shift enable
.PSINCDEC(PSINCDEC), // 1-bit input: Phase shift increment/decrement
// Feedback inputs: Clock feedback ports
.CLKFBIN(CLKFBIN) // 1-bit input: Feedback clock
);
// End of MMCME3_ADV_inst instantiation
Related Information
- See the UltraScale Architecture Clocking Resources User Guide (UG572).