Primitive: Output SERial/DESerializer
- PRIMITIVE_GROUP: I/O
- PRIMITIVE_SUBGROUP: SERDES
- Families: UltraScale, UltraScale+
Introduction
In component mode, the OSERDESE3 in UltraScale devices is a dedicated parallel-to-serial converter with specific clocking and logic features designed to facilitate the implementation of high-speed source-synchronous applications. The OSERDESE3 avoids the additional timing complexities encountered when designing serializers in the internal device logic. The OSERDESE3 can serialize an outgoing signal by 4 in SDR mode, or by 4 and 8 in DDR mode.
Port Descriptions
Port | Direction | Width | Function |
---|---|---|---|
CLK | Input | 1 | The high-speed clock input (CLK) is used to clock out the output serial data stream. |
CLKDIV | Input | 1 | The divided clock input (CLKDIV) is typically a divided version of CLK (depending on the width of the implemented serialization). It drives the input of the parallel-to-serial converter and the CE module. |
D<7:0> | Input | 8 | The parallel input data port (D) is the parallel data input port of the OSERDESE3. |
OQ | Output | 1 | Serial Output Data to the IOB |
RST | Input | 1 | Asynchronous Reset, active level based on IS_RST_INVERTED. |
T | Input | 1 | Tristate input from fabric. |
T_OUT | Output | 1 | 3-state control output to IOB. |
Design Entry Method
Instantiation | Yes |
Inference | No |
IP and IP Integrator Catalog | Yes |
Available Attributes
Attribute | Type | Allowed Values | Default | Description |
---|---|---|---|---|
DATA_WIDTH | DECIMAL | 8, 4 | 8 | Defines the width of the parallel-to-serial converter. When used with SDR clocking, the DATA_WIDTH is set to be twice the desired width. |
INIT | BINARY | 1'b0, 1'b1 | 1'b0 | Initializes the OSERDES flip-flops to the value specified. |
IS_CLKDIV_INVERTED | BINARY | 1'b0 to 1'b1 | 1'b0 | Specifies whether the CLKDIV pin is active-High or active-Low. |
IS_CLK_INVERTED | BINARY | 1'b0 to 1'b1 | 1'b0 | Specifies whether the CLK pin is active-High or active-Low. |
IS_RST_INVERTED | BINARY | 1'b0 to 1'b1 | 1'b0 | Specifies whether the RST pin is active-High or active-Low. |
ODDR_MODE | STRING | "FALSE", "TRUE" | "FALSE" | Internal property for Vivado primitive mapping. Do not modify. |
SIM_DEVICE | STRING | "7SERIES", "ULTRASCALE" | "ULTRASCALE" | Set the device version for simulation functionality. |
VHDL Instantiation Template
Unless they already exist, copy the following
two statements and paste them before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;
-- OSERDESE3: Output SERial/DESerializer
-- UltraScale
-- Xilinx HDL Language Template, version 2022.2
OSERDESE3_inst : OSERDESE3
generic map (
DATA_WIDTH => 8, -- Parallel Data Width (4-8)
INIT => '0', -- Initialization value of the OSERDES flip-flops
IS_CLKDIV_INVERTED => '0', -- Optional inversion for CLKDIV
IS_CLK_INVERTED => '0', -- Optional inversion for CLK
IS_RST_INVERTED => '0', -- Optional inversion for RST
SIM_DEVICE => "ULTRASCALE_PLUS" -- Set the device version for simulation functionality (ULTRASCALE,
-- ULTRASCALE_PLUS, ULTRASCALE_PLUS_ES1, ULTRASCALE_PLUS_ES2)
)
port map (
OQ => OQ, -- 1-bit output: Serial Output Data
T_OUT => T_OUT, -- 1-bit output: 3-state control output to IOB
CLK => CLK, -- 1-bit input: High-speed clock
CLKDIV => CLKDIV, -- 1-bit input: Divided Clock
D => D, -- 8-bit input: Parallel Data Input
RST => RST, -- 1-bit input: Asynchronous Reset
T => T -- 1-bit input: Tristate input from fabric
);
-- End of OSERDESE3_inst instantiation
Verilog Instantiation Template
// OSERDESE3: Output SERial/DESerializer
// UltraScale
// Xilinx HDL Language Template, version 2022.2
OSERDESE3 #(
.DATA_WIDTH(8), // Parallel Data Width (4-8)
.INIT(1'b0), // Initialization value of the OSERDES flip-flops
.IS_CLKDIV_INVERTED(1'b0), // Optional inversion for CLKDIV
.IS_CLK_INVERTED(1'b0), // Optional inversion for CLK
.IS_RST_INVERTED(1'b0), // Optional inversion for RST
.SIM_DEVICE("ULTRASCALE_PLUS") // Set the device version for simulation functionality (ULTRASCALE,
// ULTRASCALE_PLUS, ULTRASCALE_PLUS_ES1, ULTRASCALE_PLUS_ES2)
)
OSERDESE3_inst (
.OQ(OQ), // 1-bit output: Serial Output Data
.T_OUT(T_OUT), // 1-bit output: 3-state control output to IOB
.CLK(CLK), // 1-bit input: High-speed clock
.CLKDIV(CLKDIV), // 1-bit input: Divided Clock
.D(D), // 8-bit input: Parallel Data Input
.RST(RST), // 1-bit input: Asynchronous Reset
.T(T) // 1-bit input: Tristate input from fabric
);
// End of OSERDESE3_inst instantiation
Related Information
- See the UltraScale Architecture SelectIO Resources User Guide (UG571).