Primitive: Boundary-Scan User Instruction
- PRIMITIVE_GROUP: CONFIGURATION
- PRIMITIVE_SUBGROUP: BSCAN
- Families: UltraScale, UltraScale+
Introduction
This design element allows access to and from internal logic by the JTAG Boundary Scan logic controller. This allows for communication between the internal running design and the dedicated JTAG pins of the device. Each instance of this design element will handle one JTAG USER instruction (USER1 through USER4) as set with the JTAG_CHAIN attribute.
To handle all four USER instructions, instantiate four of these elements and set the JTAG_CHAIN attribute appropriately.
For specific information on boundary scan for an architecture, see the Configuration User Guide for the specific device.
Port Descriptions
Port | Direction | Width | Function |
---|---|---|---|
CAPTURE | Output | 1 | CAPTURE output from TAP controller. |
DRCK | Output | 1 | Gated TCK output. When SEL is asserted, DRCK toggles when CAPTURE or SHIFT are asserted. |
INTERNAL_TCK | Internal | 1 | Internal clock pin for timing. UltraScale+ only |
RESET | Output | 1 | Reset output for TAP controller. |
RUNTEST | Output | 1 | Output asserted when TAP controller is in Run Test/Idle state. |
SEL | Output | 1 | USER instruction active output. |
SHIFT | Output | 1 | SHIFT output from TAP controller. |
TCK | Output | 1 | Test Clock output. Fabric connection to TAP Clock pin. |
TDI | Output | 1 | Test Data Input (TDI) output from TAP controller. |
TDO | Input | 1 | Test Data Output (TDO) input for USER function. |
TMS | Output | 1 | Test Mode Select output. Fabric connection to TAP. |
UPDATE | Output | 1 | UPDATE output from TAP controller. |
Design Entry Method
Instantiation | Recommended |
Inference | No |
IP and IP Integrator Catalog | No |
Available Attributes
Attribute | Type | Allowed Values | Default | Description |
---|---|---|---|---|
JTAG_CHAIN | DECIMAL | 1, 2, 3, 4 | 1 | Value for USER command |
VHDL Instantiation Template
Unless they already exist, copy the following
two statements and paste them before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;
-- BSCANE2: Boundary-Scan User Instruction
-- UltraScale
-- Xilinx HDL Language Template, version 2022.2
BSCANE2_inst : BSCANE2
generic map (
JTAG_CHAIN => 1 -- Value for USER command
)
port map (
CAPTURE => CAPTURE, -- 1-bit output: CAPTURE output from TAP controller.
DRCK => DRCK, -- 1-bit output: Gated TCK output. When SEL is asserted, DRCK toggles when CAPTURE or
-- SHIFT are asserted.
RESET => RESET, -- 1-bit output: Reset output for TAP controller.
RUNTEST => RUNTEST, -- 1-bit output: Output asserted when TAP controller is in Run Test/Idle state.
SEL => SEL, -- 1-bit output: USER instruction active output.
SHIFT => SHIFT, -- 1-bit output: SHIFT output from TAP controller.
TCK => TCK, -- 1-bit output: Test Clock output. Fabric connection to TAP Clock pin.
TDI => TDI, -- 1-bit output: Test Data Input (TDI) output from TAP controller.
TMS => TMS, -- 1-bit output: Test Mode Select output. Fabric connection to TAP.
UPDATE => UPDATE, -- 1-bit output: UPDATE output from TAP controller.
TDO => TDO -- 1-bit input: Test Data Output (TDO) input for USER function.
);
-- End of BSCANE2_inst instantiation
Verilog Instantiation Template
// BSCANE2: Boundary-Scan User Instruction
// UltraScale
// Xilinx HDL Language Template, version 2022.2
BSCANE2 #(
.JTAG_CHAIN(1) // Value for USER command
)
BSCANE2_inst (
.CAPTURE(CAPTURE), // 1-bit output: CAPTURE output from TAP controller.
.DRCK(DRCK), // 1-bit output: Gated TCK output. When SEL is asserted, DRCK toggles when CAPTURE or
// SHIFT are asserted.
.RESET(RESET), // 1-bit output: Reset output for TAP controller.
.RUNTEST(RUNTEST), // 1-bit output: Output asserted when TAP controller is in Run Test/Idle state.
.SEL(SEL), // 1-bit output: USER instruction active output.
.SHIFT(SHIFT), // 1-bit output: SHIFT output from TAP controller.
.TCK(TCK), // 1-bit output: Test Clock output. Fabric connection to TAP Clock pin.
.TDI(TDI), // 1-bit output: Test Data Input (TDI) output from TAP controller.
.TMS(TMS), // 1-bit output: Test Mode Select output. Fabric connection to TAP.
.UPDATE(UPDATE), // 1-bit output: UPDATE output from TAP controller.
.TDO(TDO) // 1-bit input: Test Data Output (TDO) input for USER function.
);
// End of BSCANE2_inst instantiation
Related Information
- See the UltraScale Architecture Configuration User Guide (UG570).