Primitive: Gigabit Transceiver Buffer
- PRIMITIVE_GROUP: ADVANCED
- PRIMITIVE_SUBGROUP: GT
- Families: UltraScale
Introduction
IBUFDS_GTE3 is the gigabit transceiver input pad buffer component. The REFCLK signal should be routed to the dedicated reference clock input pins on the serial transceiver, and the user design should instantiate the IBUFDS_GTE3 primitive in the user design. See the Transceivers User Guide for more information on PCB layout requirements, including reference clock requirements.
Port Descriptions
Port | Direction | Width | Function |
---|---|---|---|
CEB | Input | 1 | Refer to Transceiver User Guide. |
I | Input | 1 | Refer to Transceiver User Guide. |
IB | Input | 1 | Refer to Transceiver User Guide. |
O | Output | 1 | Refer to Transceiver User Guide. |
ODIV2 | Output | 1 | Refer to Transceiver User Guide. |
Design Entry Method
Instantiation | Yes |
Inference | No |
IP and IP Integrator Catalog | Recommended |
Available Attributes
Attribute | Type | Allowed Values | Default | Description |
---|---|---|---|---|
REFCLK_EN_TX_PATH | BINARY | 1'b0 to 1'b1 | 1'b0 | Refer to Transceiver User Guide. |
REFCLK_HROW_CK_SEL | BINARY | 2'b00 to 2'b11 | 2'b00 | Refer to Transceiver User Guide. |
REFCLK_ICNTL_RX | BINARY | 2'b00 to 2'b11 | 2'b00 | Refer to Transceiver User Guide. |
VHDL Instantiation Template
Unless they already exist, copy the following
two statements and paste them before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;
-- IBUFDS_GTE3: Gigabit Transceiver Buffer
-- UltraScale
-- Xilinx HDL Language Template, version 2022.2
IBUFDS_GTE3_inst : IBUFDS_GTE3
generic map (
REFCLK_EN_TX_PATH => '0', -- Refer to Transceiver User Guide.
REFCLK_HROW_CK_SEL => "00", -- Refer to Transceiver User Guide.
REFCLK_ICNTL_RX => "00" -- Refer to Transceiver User Guide.
)
port map (
O => O, -- 1-bit output: Refer to Transceiver User Guide.
ODIV2 => ODIV2, -- 1-bit output: Refer to Transceiver User Guide.
CEB => CEB, -- 1-bit input: Refer to Transceiver User Guide.
I => I, -- 1-bit input: Refer to Transceiver User Guide.
IB => IB -- 1-bit input: Refer to Transceiver User Guide.
);
-- End of IBUFDS_GTE3_inst instantiation
Verilog Instantiation Template
// IBUFDS_GTE3: Gigabit Transceiver Buffer
// UltraScale
// Xilinx HDL Language Template, version 2022.2
IBUFDS_GTE3 #(
.REFCLK_EN_TX_PATH(1'b0), // Refer to Transceiver User Guide.
.REFCLK_HROW_CK_SEL(2'b00), // Refer to Transceiver User Guide.
.REFCLK_ICNTL_RX(2'b00) // Refer to Transceiver User Guide.
)
IBUFDS_GTE3_inst (
.O(O), // 1-bit output: Refer to Transceiver User Guide.
.ODIV2(ODIV2), // 1-bit output: Refer to Transceiver User Guide.
.CEB(CEB), // 1-bit input: Refer to Transceiver User Guide.
.I(I), // 1-bit input: Refer to Transceiver User Guide.
.IB(IB) // 1-bit input: Refer to Transceiver User Guide.
);
// End of IBUFDS_GTE3_inst instantiation