SYSMONE1 - 2022.2 English

UltraScale Architecture Libraries Guide (UG974)
Document ID
UG974
Release Date
2022-10-19
Version
2022.2 English

Primitive: Xilinx Analog-to-Digital Converter and System Monitor

  • PRIMITIVE_GROUP: ADVANCED
  • PRIMITIVE_SUBGROUP: SYSMON
  • Families: UltraScale, UltraScale+

Introduction

SYSMON provides an analog-to-digital conversion and associated monitoring capability. The core ADC comprises a 10-bit, 0.2 MSPS (Mega-sample-per-second) ADC, providing a general purpose analog interface for a range of applications. The ADC supports a range of operating modes and various analog input signal types (that is, unipolar, differential, etc.). The System Monitor also includes a number of on-chip sensors that support measurement of the on-chip power supply voltages and die temperature.

Port Descriptions

Port Direction Width Function
ALARMS: SYSMON alarm ports.
ALM<15:0> Output 16 Output alarm for temperature, Vccint, Vccaux and Vccbram.
  • ALM[0]: System Monitor temperature sensor alarm output.
  • ALM[1]: System Monitor Vccint sensor alarm output.
  • ALM[2]: System Monitor Vccaux sensor alarm output.
  • ALM[3]: System Monitor Vccbram sensor alarm output.
  • ALM[6:4]: Not defined.
  • ALM[7]: Logic OR of bus ALM[6:0]. Can be used to flag occurrence of any alarm.
  • ALM[11:8]: Alarms for the User Supplies 1-4.
  • ALM[14:12]: Not defined.
  • ALM[15]: Logical OR of bus ALM[14:8] which can be used to flag any alarm in this group.
OT Output 1 Over-Temperature alarm
Auxiliary Analog-Input Pairs: Sixteen auxiliary analog input pairs. In addition to the dedicated differential analog input, SYSMON can access 16 differential analog inputs by configuring digital I/O as analog inputs. These inputs can also be enabled preconfiguration via the JTAG port.
VAUXN<15:0> Input 16 N-side auxiliary analog input.
VAUXP<15:0> Input 16 P-side auxiliary analog input.
CONTROL and CLOCK: SYSMON reset, conversion start and clock inputs.
CONVST Input 1 Convert start input. This input controls the sampling instant on the SYSMON(s) input and is only used in event mode timing. This input comes from the general-purpose interconnect in the device logic.
CONVSTCLK Input 1 Convert start clock input. This input is connected to a clock net. Like CONVST, this input controls the sampling instant on the SYSMON(s) inputs and is only used in event mode timing. This input comes from the local clock distribution network in the device logic. Thus, for the best control over the sampling instant (delay and jitter), a global clock input can be used as the CONVST source.
RESET Input 1 Reset signal for the SYSMON control logic.
Dedicated Analog Input Pair: One dedicated analog input pair. SYSMON has one pair of dedicated analog input pins that provide a differential analog input. If you are designing with SYSMON but not using the dedicated external channel of VP and VN, connect both VP and VN to analog ground.
VN Input 1 N-side analog input.
VP Input 1 P-side analog input.
Dynamic Reconfiguration Port (DRP): Dynamic Reconfiguration Ports, ports used to access and control the System Monitor block.
DADDR<7:0> Input 8 Address bus for the dynamic reconfiguration port.
DCLK Input 1 Clock input for the dynamic reconfiguration port.
DEN Input 1 Enable signal for the dynamic reconfiguration port.
DI<15:0> Input 16 Input data bus for the dynamic reconfiguration port.
DO<15:0> Output 16 Output data bus for dynamic reconfiguration port.
DRDY Output 1 Data ready signal for the dynamic reconfiguration port.
DWE Input 1 Write enable for the dynamic reconfiguration port.
I2C Interface: Ports used with the I2C DRP interface.
I2C_SCLK Input 1 Input for the I2C_SCLK. Required for DRP I2C interface. The I2C_SCLK_IN and the I2C_SCLK_TS ports must be connected to the dedicated I2C_SCLK package pin as described in the UltraScale Architecture System Monitor User Guide (UG580).
I2C_SCLK_TS Output 1 Output for the I2C_SCLK. Required for DRP I2C interface. The I2C_SCLK_IN and the I2C_SCLK_TS ports must be connected to the dedicated I2C_SCLK package pin as described in the UltraScale Architecture System Monitor User Guide (UG580).
I2C_SDA Input 1 Input for the I2C_SDA. Required for DRP I2C interface. The I2C_SDA_IN and the I2C_SDA_TS ports must be connected to the dedicated I2C_SDA package pin as described in the UltraScale Architecture System Monitor User Guide (UG580).
I2C_SDA_TS Output 1 Output for the I2C_SDA. Required for DRP I2C interface. The I2C_SDA_IN and the I2C_SDA_TS ports must be connected to the dedicated I2C_SDA package pin as described in the UltraScale Architecture System Monitor User Guide (UG580).
STATUS: SYSMON status ports.
BUSY Output 1 SYSMON busy signal. This signal transitions High during an ADC conversion. This signal also transitions High for an extended period during an ADC or sensor calibration.
CHANNEL<5:0> Output 6 Channel selection outputs. The SYSMON input MUX channel selection for the current ADC conversion is placed on these outputs at the end of an ADC conversion.
EOC Output 1 End of Conversion signal. This signal transitions to an active-High at the end of an ADC conversion when the measurement is written to the status registers.
EOS Output 1 End of Sequence. This signal transitions to active-High when the measurement data from the last channel in an automatic channel sequence is written to the status registers.
JTAGBUSY Output 1 Used to indicate that a JTAG DRP transaction is in progress.
JTAGLOCKED Output 1 Indicates that a DRP port lock request has been made by the JTAG interface. This signal is also used to indicate that the DRP is ready for access (when Low).
JTAGMODIFIED Output 1 Used to indicate that a JTAG Write to the DRP has occurred.
MUXADDR<4:0> Output 5 These outputs are used in external multiplexer mode. They indicate the address of the next channel in a sequence to be converted. They provide the channel address for an external multiplexer.

Design Entry Method

Instantiation Yes
Inference No
IP and IP Integrator Catalog Recommended

Available Attributes

Attribute Type Allowed Values Default Description
INIT_45 HEX 16'h0000 to 16'hffff 16'h0000 Analog Bus Register
INIT_40 - INIT_44: System Monitor configuration registers.
INIT_40 HEX 16'h0000 to 16'hffff 16'h0000 Configuration register 0.
INIT_41 HEX 16'h0000 to 16'hffff 16'h0000 Configuration register 1.
INIT_42 HEX 16'h0000 to 16'hffff 16'h0000 Configuration register 2.
INIT_43 HEX 16'h0000 to 16'hffff 16'h0000 Configuration register 3.
INIT_44 HEX 16'h0000 to 16'hffff 16'h0000 Configuration register 4.
INIT_46 - INIT_4F: Sequence registers used to program the System Monitor Channel.
INIT_4A HEX 16'h0000 to 16'hffff 16'h0000 Sequence register 4.
INIT_4B HEX 16'h0000 to 16'hffff 16'h0000 Sequence register 5.
INIT_4C HEX 16'h0000 to 16'hffff 16'h0000 Sequence register 6.
INIT_4D HEX 16'h0000 to 16'hffff 16'h0000 Sequence register 7.
INIT_4E HEX 16'h0000 to 16'hffff 16'h0000 Sequence register 8.
INIT_4F HEX 16'h0000 to 16'hffff 16'h0000 Sequence register 9.
INIT_46 HEX 16'h0000 to 16'hffff 16'h0000 Sequence register 0.
INIT_47 HEX 16'h0000 to 16'hffff 16'h0000 Sequence register 1.
INIT_48 HEX 16'h0000 to 16'hffff 16'h0000 Sequence register 2.
INIT_49 HEX 16'h0000 to 16'hffff 16'h0000 Sequence register 3.
INIT_50 - INIT_5F: Alarm threshold registers for the System Monitor alarm function.
INIT_5A HEX 16'h0000 to 16'hffff 16'h0000 Alarm limit register 10.
INIT_5B HEX 16'h0000 to 16'hffff 16'h0000 Alarm limit register 11.
INIT_5C HEX 16'h0000 to 16'hffff 16'h0000 Alarm limit register 12.
INIT_5D HEX 16'h0000 to 16'hffff 16'h0000 Alarm limit register 13.
INIT_5E HEX 16'h0000 to 16'hffff 16'h0000 Alarm limit register 14.
INIT_5F HEX 16'h0000 to 16'hffff 16'h0000 Alarm limit register 15.
INIT_50 HEX 16'h0000 to 16'hffff 16'h0000 Alarm limit register 0.
INIT_51 HEX 16'h0000 to 16'hffff 16'h0000 Alarm limit register 1.
INIT_52 HEX 16'h0000 to 16'hffff 16'h0000 Alarm limit register 2.
INIT_53 HEX 16'h0000 to 16'hffff 16'h0000 Alarm limit register 3.
INIT_54 HEX 16'h0000 to 16'hffff 16'h0000 Alarm limit register 4.
INIT_55 HEX 16'h0000 to 16'hffff 16'h0000 Alarm limit register 5.
INIT_56 HEX 16'h0000 to 16'hffff 16'h0000 Alarm limit register 6.
INIT_57 HEX 16'h0000 to 16'hffff 16'h0000 Alarm limit register 7.
INIT_58 HEX 16'h0000 to 16'hffff 16'h0000 Alarm limit register 8.
INIT_59 HEX 16'h0000 to 16'hffff 16'h0000 Alarm limit register 9.
INIT_60 - INIT_6F: User supply alarms.
INIT_6A HEX 16'h0000 to 16'hffff 16'h0000 User supply alarm register 10.
INIT_6B HEX 16'h0000 to 16'hffff 16'h0000 User supply alarm register 11.
INIT_6C HEX 16'h0000 to 16'hffff 16'h0000 User supply alarm register 12.
INIT_6D HEX 16'h0000 to 16'hffff 16'h0000 User supply alarm register 13.
INIT_6E HEX 16'h0000 to 16'hffff 16'h0000 User supply alarm register 14.
INIT_6F HEX 16'h0000 to 16'hffff 16'h0000 User supply alarm register 15.
INIT_60 HEX 16'h0000 to 16'hffff 16'h0000 User supply alarm register 0.
INIT_61 HEX 16'h0000 to 16'hffff 16'h0000 User supply alarm register 1.
INIT_62 HEX 16'h0000 to 16'hffff 16'h0000 User supply alarm register 2.
INIT_63 HEX 16'h0000 to 16'hffff 16'h0000 User supply alarm register 3.
INIT_64 HEX 16'h0000 to 16'hffff 16'h0000 User supply alarm register 4.
INIT_65 HEX 16'h0000 to 16'hffff 16'h0000 User supply alarm register 5.
INIT_66 HEX 16'h0000 to 16'hffff 16'h0000 User supply alarm register 6.
INIT_67 HEX 16'h0000 to 16'hffff 16'h0000 User supply alarm register 7.
INIT_68 HEX 16'h0000 to 16'hffff 16'h0000 User supply alarm register 8.
INIT_69 HEX 16'h0000 to 16'hffff 16'h0000 User supply alarm register 9.
INIT_73 - INIT_77: System Monitor Test registers not for customer usage.
INIT_73 HEX 16'h0000 to 16'hffff 16'h0000 System Monitor Test registers not for customer usage.
INIT_74 HEX 16'h0000 to 16'hffff 16'h0000 System Monitor Test registers not for customer usage.
INIT_75 HEX 16'h0000 to 16'hffff 16'h0000 System Monitor Test registers not for customer usage.
INIT_76 HEX 16'h0000 to 16'hffff 16'h0000 System Monitor Test registers not for customer usage.
INIT_77 HEX 16'h0000 to 16'hffff 16'h0000 System Monitor Test registers not for customer usage.
Not Defined: Parameters not defined and reserved for future use.
INIT_7A HEX 16'h0000 to 16'hffff 16'h0000 Reserved for future use.
INIT_7B HEX 16'h0000 to 16'hffff 16'h0000 Reserved for future use.
INIT_7C HEX 16'h0000 to 16'hffff 16'h0000 Reserved for future use.
INIT_7D HEX 16'h0000 to 16'hffff 16'h0000 Reserved for future use.
INIT_7E HEX 16'h0000 to 16'hffff 16'h0000 Reserved for future use.
INIT_7F HEX 16'h0000 to 16'hffff 16'h0000 Reserved for future use.
INIT_70 HEX 16'h0000 to 16'hffff 16'h0000 Reserved for future use.
INIT_71 HEX 16'h0000 to 16'hffff 16'h0000 Reserved for future use.
INIT_72 HEX 16'h0000 to 16'hffff 16'h0000 Reserved for future use.
INIT_78 HEX 16'h0000 to 16'hffff 16'h0000 Reserved for future use.
INIT_79 HEX 16'h0000 to 16'hffff 16'h0000 Reserved for future use.
Programmable Inversion Attributes: Indicates whether or not to use the optional inversions on specific pins of this component to change the active polarity of the pin function. When set to 1 on a clock pin, this components clocks on the negative edge. When set to 1 on other pins, it changes the function to behave active-Low rather than active-High. For pins that are buses, the bit-width of this attribute should match that of the bit-width of the associated pins and a binary value indicates which inverters to use and which to bypass. If an external inverter is specified on one of these associated pins, the Vivado Design Suite will automatically set this attribute during the opt_design stage so that additional logic is not necessary for changing the input polarity.
IS_CONVSTCLK_INVERTED BINARY 1'b0 to 1'b1 1'b0 Specifies whether or not to use the optional inversion on the CONVSTCLK pin of this component.
IS_DCLK_INVERTED BINARY 1'b0 to 1'b1 1'b0 Specifies whether or not to use the optional inversion on the DCLK pin of this component.
Simulation attributes: Specify the following attributes to allow for proper simulation of the System Monitor block.
SIM_MONITOR_FILE STRING String "design.txt" Specify the file name (and directory if different from simulation directory) of file containing analog voltage and temperature data for SYSMON simulation behavior.
User Voltage Monitor: SYSMON User voltage monitor attributes.
SYSMON_VUSER0_BANK DECIMAL 0 to 999 0 Specify the I/O Bank number to be used with User0 for monitoring.
SYSMON_VUSER0_MONITOR STRING String "NONE" Specify the voltage to monitor for User0.
SYSMON_VUSER1_BANK DECIMAL 0 to 999 0 Specify the I/O Bank number to be used with User1 for monitoring.
SYSMON_VUSER1_MONITOR STRING String "NONE" Specify the voltage to monitor for User1.
SYSMON_VUSER2_BANK DECIMAL 0 to 999 0 Specify the I/O Bank number to be used with User2 for monitoring.
SYSMON_VUSER2_MONITOR STRING String "NONE" Specify the voltage to monitor for User2.
SYSMON_VUSER3_BANK DECIMAL 0 to 999 0 Specify the I/O Bank number to be used with User3 for monitoring.
SYSMON_VUSER3_MONITOR STRING String "NONE" Specify the voltage to monitor for User3.

VHDL Instantiation Template

Unless they already exist, copy the following two statements and paste them before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;

-- SYSMONE1: Xilinx Analog-to-Digital Converter and System Monitor
--           UltraScale
-- Xilinx HDL Language Template, version 2022.2

SYSMONE1_inst : SYSMONE1
generic map (
   -- INIT_40 - INIT_44: SYSMON configuration registers
   INIT_40 => X"0000",
   INIT_41 => X"0000",
   INIT_42 => X"0000",
   INIT_43 => X"0000",
   INIT_44 => X"0000",
   INIT_45 => X"0000",               -- Analog Bus Register
   -- INIT_46 - INIT_4F: Sequence Registers
   INIT_46 => X"0000",
   INIT_47 => X"0000",
   INIT_48 => X"0000",
   INIT_49 => X"0000",
   INIT_4A => X"0000",
   INIT_4B => X"0000",
   INIT_4C => X"0000",
   INIT_4D => X"0000",
   INIT_4E => X"0000",
   INIT_4F => X"0000",
   -- INIT_50 - INIT_5F: Alarm Limit Registers
   INIT_50 => X"0000",
   INIT_51 => X"0000",
   INIT_52 => X"0000",
   INIT_53 => X"0000",
   INIT_54 => X"0000",
   INIT_55 => X"0000",
   INIT_56 => X"0000",
   INIT_57 => X"0000",
   INIT_58 => X"0000",
   INIT_59 => X"0000",
   INIT_5A => X"0000",
   INIT_5B => X"0000",
   INIT_5C => X"0000",
   INIT_5D => X"0000",
   INIT_5E => X"0000",
   INIT_5F => X"0000",
   -- INIT_60 - INIT_6F: User Supply Alarms
   INIT_60 => X"0000",
   INIT_61 => X"0000",
   INIT_62 => X"0000",
   INIT_63 => X"0000",
   INIT_64 => X"0000",
   INIT_65 => X"0000",
   INIT_66 => X"0000",
   INIT_67 => X"0000",
   INIT_68 => X"0000",
   INIT_69 => X"0000",
   INIT_6A => X"0000",
   INIT_6B => X"0000",
   INIT_6C => X"0000",
   INIT_6D => X"0000",
   INIT_6E => X"0000",
   INIT_6F => X"0000",
   -- Programmable Inversion Attributes: Specifies the use of the built-in programmable inversion on
   -- specific pins
   IS_CONVSTCLK_INVERTED => '0',     -- Optional inversion for CONVSTCLK, 0-1
   IS_DCLK_INVERTED => '0',          -- Optional inversion for DCLK, 0-1
   -- Simulation attributes: Set for proper simulation behavior
   SIM_MONITOR_FILE => "design.txt", -- Analog simulation data file name
   -- User Voltage Monitor: SYSMON User voltage monitor
   SYSMON_VUSER0_BANK => 0,          -- Specify IO Bank for User0
   SYSMON_VUSER0_MONITOR => "NONE",  -- Specify Voltage for User0
   SYSMON_VUSER1_BANK => 0,          -- Specify IO Bank for User1
   SYSMON_VUSER1_MONITOR => "NONE",  -- Specify Voltage for User1
   SYSMON_VUSER2_BANK => 0,          -- Specify IO Bank for User2
   SYSMON_VUSER2_MONITOR => "NONE",  -- Specify Voltage for User2
   SYSMON_VUSER3_MONITOR => "NONE"   -- Specify Voltage for User3
)
port map (
   -- ALARMS outputs: ALM, OT
   ALM => ALM,                   -- 16-bit output: Output alarm for temp, Vccint, Vccaux and Vccbram
   OT => OT,                     -- 1-bit output: Over-Temperature alarm
   -- Dynamic Reconfiguration Port (DRP) outputs: Dynamic Reconfiguration Ports
   DO => DO,                     -- 16-bit output: DRP output data bus
   DRDY => DRDY,                 -- 1-bit output: DRP data ready
   -- I2C Interface outputs: Ports used with the I2C DRP interface
   I2C_SCLK_TS => I2C_SCLK_TS,   -- 1-bit output: I2C_SCLK output port
   I2C_SDA_TS => I2C_SDA_TS,     -- 1-bit output: I2C_SDA_TS output port
   -- STATUS outputs: SYSMON status ports
   BUSY => BUSY,                 -- 1-bit output: System Monitor busy output
   CHANNEL => CHANNEL,           -- 6-bit output: Channel selection outputs
   EOC => EOC,                   -- 1-bit output: End of Conversion
   EOS => EOS,                   -- 1-bit output: End of Sequence
   JTAGBUSY => JTAGBUSY,         -- 1-bit output: JTAG DRP transaction in progress output
   JTAGLOCKED => JTAGLOCKED,     -- 1-bit output: JTAG requested DRP port lock
   JTAGMODIFIED => JTAGMODIFIED, -- 1-bit output: JTAG Write to the DRP has occurred
   MUXADDR => MUXADDR,           -- 5-bit output: External MUX channel decode
   -- Auxiliary Analog-Input Pairs inputs: VAUXP[15:0], VAUXN[15:0]
   VAUXN => VAUXN,               -- 16-bit input: N-side auxiliary analog input
   VAUXP => VAUXP,               -- 16-bit input: P-side auxiliary analog input
   -- CONTROL and CLOCK inputs: Reset, conversion start and clock inputs
   CONVST => CONVST,             -- 1-bit input: Convert start input
   CONVSTCLK => CONVSTCLK,       -- 1-bit input: Convert start input
   RESET => RESET,               -- 1-bit input: Active-High reset
   -- Dedicated Analog Input Pair inputs: VP/VN
   VN => VN,                     -- 1-bit input: N-side analog input
   VP => VP,                     -- 1-bit input: P-side analog input
   -- Dynamic Reconfiguration Port (DRP) inputs: Dynamic Reconfiguration Ports
   DADDR => DADDR,               -- 8-bit input: DRP address bus
   DCLK => DCLK,                 -- 1-bit input: DRP clock
   DEN => DEN,                   -- 1-bit input: DRP enable signal
   DI => DI,                     -- 16-bit input: DRP input data bus
   DWE => DWE,                   -- 1-bit input: DRP write enable
   -- I2C Interface inputs: Ports used with the I2C DRP interface
   I2C_SCLK => I2C_SCLK,         -- 1-bit input: I2C_SCLK input port
   I2C_SDA => I2C_SDA            -- 1-bit input: I2C_SDA input port
);

-- End of SYSMONE1_inst instantiation

Verilog Instantiation Template


// SYSMONE1: Xilinx Analog-to-Digital Converter and System Monitor
//           UltraScale
// Xilinx HDL Language Template, version 2022.2

SYSMONE1 #(
   // INIT_40 - INIT_44: SYSMON configuration registers
   .INIT_40(16'h0000),
   .INIT_41(16'h0000),
   .INIT_42(16'h0000),
   .INIT_43(16'h0000),
   .INIT_44(16'h0000),
   .INIT_45(16'h0000),              // Analog Bus Register
   // INIT_46 - INIT_4F: Sequence Registers
   .INIT_46(16'h0000),
   .INIT_47(16'h0000),
   .INIT_48(16'h0000),
   .INIT_49(16'h0000),
   .INIT_4A(16'h0000),
   .INIT_4B(16'h0000),
   .INIT_4C(16'h0000),
   .INIT_4D(16'h0000),
   .INIT_4E(16'h0000),
   .INIT_4F(16'h0000),
   // INIT_50 - INIT_5F: Alarm Limit Registers
   .INIT_50(16'h0000),
   .INIT_51(16'h0000),
   .INIT_52(16'h0000),
   .INIT_53(16'h0000),
   .INIT_54(16'h0000),
   .INIT_55(16'h0000),
   .INIT_56(16'h0000),
   .INIT_57(16'h0000),
   .INIT_58(16'h0000),
   .INIT_59(16'h0000),
   .INIT_5A(16'h0000),
   .INIT_5B(16'h0000),
   .INIT_5C(16'h0000),
   .INIT_5D(16'h0000),
   .INIT_5E(16'h0000),
   .INIT_5F(16'h0000),
   // INIT_60 - INIT_6F: User Supply Alarms
   .INIT_60(16'h0000),
   .INIT_61(16'h0000),
   .INIT_62(16'h0000),
   .INIT_63(16'h0000),
   .INIT_64(16'h0000),
   .INIT_65(16'h0000),
   .INIT_66(16'h0000),
   .INIT_67(16'h0000),
   .INIT_68(16'h0000),
   .INIT_69(16'h0000),
   .INIT_6A(16'h0000),
   .INIT_6B(16'h0000),
   .INIT_6C(16'h0000),
   .INIT_6D(16'h0000),
   .INIT_6E(16'h0000),
   .INIT_6F(16'h0000),
   // Programmable Inversion Attributes: Specifies the use of the built-in programmable inversion on
   // specific pins
   .IS_CONVSTCLK_INVERTED(1'b0),    // Optional inversion for CONVSTCLK, 0-1
   .IS_DCLK_INVERTED(1'b0),         // Optional inversion for DCLK, 0-1
   // Simulation attributes: Set for proper simulation behavior
   .SIM_MONITOR_FILE("design.txt"), // Analog simulation data file name
   // User Voltage Monitor: SYSMON User voltage monitor
   .SYSMON_VUSER0_BANK(0),          // Specify IO Bank for User0
   .SYSMON_VUSER0_MONITOR("NONE"),  // Specify Voltage for User0
   .SYSMON_VUSER1_BANK(0),          // Specify IO Bank for User1
   .SYSMON_VUSER1_MONITOR("NONE"),  // Specify Voltage for User1
   .SYSMON_VUSER2_BANK(0),          // Specify IO Bank for User2
   .SYSMON_VUSER2_MONITOR("NONE"),  // Specify Voltage for User2
   .SYSMON_VUSER3_MONITOR("NONE")   // Specify Voltage for User3
)
SYSMONE1_inst (
   // ALARMS outputs: ALM, OT
   .ALM(ALM),                   // 16-bit output: Output alarm for temp, Vccint, Vccaux and Vccbram
   .OT(OT),                     // 1-bit output: Over-Temperature alarm
   // Dynamic Reconfiguration Port (DRP) outputs: Dynamic Reconfiguration Ports
   .DO(DO),                     // 16-bit output: DRP output data bus
   .DRDY(DRDY),                 // 1-bit output: DRP data ready
   // I2C Interface outputs: Ports used with the I2C DRP interface
   .I2C_SCLK_TS(I2C_SCLK_TS),   // 1-bit output: I2C_SCLK output port
   .I2C_SDA_TS(I2C_SDA_TS),     // 1-bit output: I2C_SDA_TS output port
   // STATUS outputs: SYSMON status ports
   .BUSY(BUSY),                 // 1-bit output: System Monitor busy output
   .CHANNEL(CHANNEL),           // 6-bit output: Channel selection outputs
   .EOC(EOC),                   // 1-bit output: End of Conversion
   .EOS(EOS),                   // 1-bit output: End of Sequence
   .JTAGBUSY(JTAGBUSY),         // 1-bit output: JTAG DRP transaction in progress output
   .JTAGLOCKED(JTAGLOCKED),     // 1-bit output: JTAG requested DRP port lock
   .JTAGMODIFIED(JTAGMODIFIED), // 1-bit output: JTAG Write to the DRP has occurred
   .MUXADDR(MUXADDR),           // 5-bit output: External MUX channel decode
   // Auxiliary Analog-Input Pairs inputs: VAUXP[15:0], VAUXN[15:0]
   .VAUXN(VAUXN),               // 16-bit input: N-side auxiliary analog input
   .VAUXP(VAUXP),               // 16-bit input: P-side auxiliary analog input
   // CONTROL and CLOCK inputs: Reset, conversion start and clock inputs
   .CONVST(CONVST),             // 1-bit input: Convert start input
   .CONVSTCLK(CONVSTCLK),       // 1-bit input: Convert start input
   .RESET(RESET),               // 1-bit input: Active-High reset
   // Dedicated Analog Input Pair inputs: VP/VN
   .VN(VN),                     // 1-bit input: N-side analog input
   .VP(VP),                     // 1-bit input: P-side analog input
   // Dynamic Reconfiguration Port (DRP) inputs: Dynamic Reconfiguration Ports
   .DADDR(DADDR),               // 8-bit input: DRP address bus
   .DCLK(DCLK),                 // 1-bit input: DRP clock
   .DEN(DEN),                   // 1-bit input: DRP enable signal
   .DI(DI),                     // 16-bit input: DRP input data bus
   .DWE(DWE),                   // 1-bit input: DRP write enable
   // I2C Interface inputs: Ports used with the I2C DRP interface
   .I2C_SCLK(I2C_SCLK),         // 1-bit input: I2C_SCLK input port
   .I2C_SDA(I2C_SDA)            // 1-bit input: I2C_SDA input port
);

// End of SYSMONE1_inst instantiation

Related Information

  • See the UltraScale Architecture System Monitor User Guide (UG580).