Primitive: Input Buffer with Offset Calibration and VREF Tuning
- PRIMITIVE_GROUP: I/O
- PRIMITIVE_SUBGROUP: INPUT_BUFFER
- Families: UltraScale, UltraScale+
Introduction
The input buffer (IBUFE3) primitive is only supported in HP I/O banks. This primitive has functions similar to the IBUF_IBUFDISABLE with added controls for offset calibration and VREF tuning, along with input buffer disable (IBUFDISABLE). The offset calibration feature is accessed using the OSC_EN and OSC[3:0] ports. The VREF scan feature is accessed using the HPIO_VREF primitive in conjunction with IBUFE3.
I/O attributes that do not impact the logic function of the component, such as IOSTANDARD, and IBUF_LOW_PWR, should be supplied in XDC or to the top-level port via an appropriate property. For details on applying such properties to the associated port, see the Vivado Design Suite Properties Reference Guide (UG912). Attributes that impact the functionality, such as SIM_INPUT_BUFFER_OFFSET, must be supplied to the component via a generic_map (VHDL) or parameter (Verilog) to have the correct simulation behavior.
Port Descriptions
Port | Direction | Width | Function |
---|---|---|---|
I | Input | 1 | Diff_p Buffer Input. Connect to top-level p-side input port. |
IBUFDISABLE | Input | 1 | Disables input path through the buffer and forces to a logic Low. This feature is generally used to reduce power at times when the I/O is idle for a period of time. |
O | Output | 1 | Buffer output |
OSC<3:0> | Input | 4 | Offset cancellation value |
OSC_EN | Input | 1 | Offset cancellation enable |
VREF | Input | 1 | Vref input from HPIO_VREF |
Design Entry Method
Instantiation | Yes |
Inference | No |
IP and IP Integrator Catalog | No |
Available Attributes
Attribute | Type | Allowed Values | Default | Description |
---|---|---|---|---|
SIM_DEVICE | STRING | "7SERIES", "ULTRASCALE" | "ULTRASCALE" | Set the device version for simulation functionality. |
SIM_INPUT_BUFFER_OFFSET | DECIMAL | -50 to 50 | 0 | Offset value for simulation purposes. |
USE_IBUFDISABLE | STRING | "FALSE", "T_CONTROL", "TRUE" | "FALSE" | Set this attribute to "TRUE" to enable the IBUFDISABLE pin. |
VHDL Instantiation Template
Library UNISIM;
use UNISIM.vcomponents.all;
-- IBUFE3: Input Buffer with Offset Calibration and VREF Tuning
-- UltraScale
-- Xilinx HDL Language Template, version 2022.2
IBUFE3_inst : IBUFE3
generic map (
CCIO_EN => "TRUE",
SIM_DEVICE => "ULTRASCALE_PLUS", -- Set the device version for simulation functionality (ULTRASCALE,
-- ULTRASCALE_PLUS)
SIM_INPUT_BUFFER_OFFSET => 0, -- Offset value for simulation (-50-50)
USE_IBUFDISABLE => "FALSE" -- Enable/Disable the IBUFDISABLE pin (FALSE, TRUE, T_CONTROL)
)
port map (
O => O, -- 1-bit output: Buffer output
I => I, -- 1-bit input: Buffer input (connect directly to top-level port)
IBUFDISABLE => IBUFDISABLE, -- 1-bit input: Buffer disable input, high=disable
OSC => OSC, -- 4-bit input: Offset cancellation value
OSC_EN => OSC_EN, -- 1-bit input: Offset cancellation enable
VREF => VREF -- 1-bit input: Vref input from HPIO_VREF
);
-- End of IBUFE3_inst instantiation
Verilog Instantiation Template
// IBUFE3: Input Buffer with Offset Calibration and VREF Tuning
// UltraScale
// Xilinx HDL Language Template, version 2022.2
IBUFE3 #(
.CCIO_EN("TRUE"),
.SIM_DEVICE("ULTRASCALE_PLUS"), // Set the device version for simulation functionality (ULTRASCALE,
// ULTRASCALE_PLUS)
.SIM_INPUT_BUFFER_OFFSET(0), // Offset value for simulation (-50-50)
.USE_IBUFDISABLE("FALSE") // Enable/Disable the IBUFDISABLE pin (FALSE, TRUE, T_CONTROL)
)
IBUFE3_inst (
.O(O), // 1-bit output: Buffer output
.I(I), // 1-bit input: Buffer input (connect directly to top-level port)
.IBUFDISABLE(IBUFDISABLE), // 1-bit input: Buffer disable input, high=disable
.OSC(OSC), // 4-bit input: Offset cancellation value
.OSC_EN(OSC_EN), // 1-bit input: Offset cancellation enable
.VREF(VREF) // 1-bit input: Vref input from HPIO_VREF
);
// End of IBUFE3_inst instantiation