CARRY8 - 2022.2 English

Primitive: Fast Carry Logic with Look Ahead

PRIMITIVE_GROUP: CLB
PRIMITIVE_SUBGROUP: CARRY
Families: UltraScale, UltraScale+

Introduction

This circuit represents the fast carry logic for a CLB. The carry chain consists of a series of eight MUXes and eight XORs that connect to the other logic (LUTs) in the CLB via dedicated routes to form more complex functions. The fast carry logic is useful for building arithmetic functions like adders, counters, subtracters, and add/subs, as well as other logic functions, such as wide comparators, address decoders, and some logic gates. This component can be configured to operate as a single 8-bit carry or two independent 4-bit carry logic.

Port Descriptions

Port	Direction	Width	Function
CI	Input	1	Carry input for 8-bit carry or lower portion of 4-bit carry.
CI_TOP	Input	1	Upper carry input when CARRY_TYPE=DUAL_CY4. Tie to ground if CARRY_TYPE=SINGLE_CY8.
CO<7:0>	Output	8	Carry-out of each stage of the carry chain.
DI<7:0>	Input	8	Carry-MUX data input.
O<7:0>	Output	8	Carry chain XOR general data out.
S<7:0>	Input	8	Carry-MUX select line.

Design Entry Method

Instantiation	Yes
Inference	Recommended
IP and IP Integrator Catalog	Yes

Available Attributes

Attribute	Type	Allowed Values	Default	Description
CARRY_TYPE	STRING	"SINGLE_CY8", "DUAL_CY4"	"SINGLE_CY8"	Specifies whether the CLB carry logic is to function as a single 8-bit carry-chain or two independent 4-bit carry chains.

VHDL Instantiation Template

Unless they already exist, copy the following two statements and paste them before the entity declaration.

Library UNISIM;
use UNISIM.vcomponents.all;


-- CARRY8: Fast Carry Logic with Look Ahead
--         UltraScale
-- Xilinx HDL Language Template, version 2022.2

CARRY8_inst : CARRY8
generic map (
   CARRY_TYPE => "SINGLE_CY8"  -- 8-bit or dual 4-bit carry (DUAL_CY4, SINGLE_CY8)
)
port map (
   CO => CO,         -- 8-bit output: Carry-out
   O => O,           -- 8-bit output: Carry chain XOR data out
   CI => CI,         -- 1-bit input: Lower Carry-In
   CI_TOP => CI_TOP, -- 1-bit input: Upper Carry-In
   DI => DI,         -- 8-bit input: Carry-MUX data in
   S => S            -- 8-bit input: Carry-mux select
);

-- End of CARRY8_inst instantiation

Verilog Instantiation Template


// CARRY8: Fast Carry Logic with Look Ahead
//         UltraScale
// Xilinx HDL Language Template, version 2022.2

CARRY8 #(
   .CARRY_TYPE("SINGLE_CY8")  // 8-bit or dual 4-bit carry (DUAL_CY4, SINGLE_CY8)
)
CARRY8_inst (
   .CO(CO),         // 8-bit output: Carry-out
   .O(O),           // 8-bit output: Carry chain XOR data out
   .CI(CI),         // 1-bit input: Lower Carry-In
   .CI_TOP(CI_TOP), // 1-bit input: Upper Carry-In
   .DI(DI),         // 8-bit input: Carry-MUX data in
   .S(S)            // 8-bit input: Carry-mux select
);

// End of CARRY8_inst instantiation

Related Information

See the UltraScale Architecture Configurable Logic Block User Guide (UG574).