This bridge type is intended for designs that use Xilinx Virtual Cable (XVC) to remotely debug an
FPGA or SoC device through Ethernet or other interfaces. In this mode, the Debug Bridge
receives XVC commands via AXI4-Lite interface to send over the JTAG pins to a target
device. For more information see the
Debug Bridge LogiCORE IP Product Guide (PG245 ) .
Figure 1. AXI to JTAG Debug Bridge
Page-1
Process.99
Target Board
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Data Center
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Zynq Processor XVC Server
XVC Server
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AXI
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hw_server
Process.507
Vivado_Logo_FINAL.23
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XVC over TCP/IP
TCP /IP
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Debug Bridge (From AXI to JTAG)
Bridge ( From AXI to JTAG )
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BSCAN
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Debug Hub
Hub
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User Responsibility
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Vivado Solution
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FPGA #2
Xilinx_Logo_corp_4C.519
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JTAG
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Debug Bridge (From JTAG to BSCAN)
Bridge ( From JTAG to BSCAN )
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Xilinx_Logo_corp_4C.76
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FPGA #1
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Debug IP 1 (eg ILA, VIO etc)
( eg ILA , VIO etc )
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……
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Debug IP n (eg ILA, VIO etc)
( eg ILA , VIO etc )
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X17966-092816