From PCIe to BSCAN - 2022.1 English

Vivado Design Suite User Guide: Programming and Debugging (UG908)
Document ID
UG908
Release Date
2022-04-26
Version
2022.1 English

In a typical PCIe setup - you can use the Debug Bridge in the PCIe to BSCAN mode to communicate with the debug cores. In this mode, Debug Bridge connects to the Extended Configuration Interface of the PCIe IP. This is a common data center use case where PCIe is the preferred communication pathway to the Host PC instead of JTAG. For more information on using the XVC flow with the PCIe core and Debug Bridge in this mode, and for an example design refer to UltraScale+ Devices Integrated Block for PCI Express LogiCORE IP Product Guide (PG213).

Figure 1. PCIe to BSCAN Debug Bridge Used with PCIe Extended Configuration Interface
Page-1 10pt. Arial Text.55 Processor XVC Server ProcessorXVC Server Sheet.12 8pt. Arial Text.69 PCIe PCIe Sheet.15 10pt. Arial Text.9 hw_server hw_server Process.17 Vivado_Logo_FINAL.23 Sheet.19 Sheet.20 Sheet.21 Sheet.22 Sheet.23 Sheet.24 Sheet.25 Sheet.26 Sheet.27 Sheet.28 8pt. Arial Text.512 XVC over TCP/IP XVC overTCP/IP Sheet.30 Process.85 8pt. Arial Text.86 PCIe (Extended Configuration) PCIe(ExtendedConfiguration) 8pt. Arial Text.88 PCIe ext cfg PCIe extcfg Sheet.35 Process.507 Debug Bridge (From AXI to BSCAN) Debug Bridge(From AXI to BSCAN) 8pt. Arial Text.91 BSCAN BSCAN Sheet.38 10pt. Arial Text.99 10pt. Arial Text.100 8pt. Arial Text.101 User Solution User Solution 8pt. Arial Text.102 Vivado Solution Vivado Solution 8pt. Arial Text.104 Target FPGA Target FPGA Process.156 Xilinx_Logo_corp_4C.519 Sheet.59 Sheet.60 Sheet.61 Sheet.62 Sheet.63 Sheet.64 Sheet.65 Sheet.66 Sheet.67 Sheet.68 Sheet.69 Sheet.70 Process.93 Debug Hub Debug Hub 8pt. Arial Text.515 Debug Core 1 Debug Core 1 Sheet.73 8pt. Arial Text.96 …… …… 8pt. Arial Text.97 Debug Core n Debug Core n Sheet.76 Sheet.50 X17962-040517 X17962-040517