From PCIe to JTAG - 2022.1 English

Vivado Design Suite User Guide: Programming and Debugging (UG908)
Document ID
UG908
Release Date
2022-04-26
Version
2022.1 English

In a PCIe setup, you can use the Debug Bridge in the PCIe to JTAG mode to communicate with the debug cores. In this mode, Debug Bridge connects to the Extended Configuration Interface of the PCIe® IP, which in turn can communicate over JTAG to the debug hub on a different target FPGA.

Figure 1. PCIe® to JTAG Debug Bridge Used with PCIe Extended Configuration Interface
Page-1 Process.99 Target Board Target Board Process.2 Process.66 10pt. Arial Text.55 PCIe Master PCIeMaster Sheet.83 8pt. Arial Text.69 PCIe ext cfg PCIe extcfg Sheet.85 Sheet.86 10pt. Arial Text.9 hw_server hw_server Process.507 Vivado_Logo_FINAL.23 Sheet.90 Sheet.91 Sheet.92 Sheet.93 Sheet.94 Sheet.95 Sheet.96 Sheet.97 Sheet.98 Sheet.99 8pt. Arial Text.512 PCIe PCIe Sheet.101 Process.507 Debug Bridge (From PCIe to JTAG) Debug Bridge(From PCIe to JTAG) Process.93 Debug Hub Debug Hub 10pt. Arial Text.99 10pt. Arial Text.100 8pt. Arial Text.101 User Responsibility User Responsibility 8pt. Arial Text.102 Vivado Solution Vivado Solution 8pt. Arial Text.104 FPGA #2 FPGA #2 Xilinx_Logo_corp_4C.519 Sheet.112 Sheet.113 Sheet.114 Sheet.115 Sheet.116 Sheet.117 Sheet.118 Sheet.119 Sheet.120 Sheet.121 Sheet.122 Sheet.123 8pt. Arial Text.65 JTAG JTAG Sheet.125 8pt. Arial Text.75 Xilinx_Logo_corp_4C.76 Sheet.129 Sheet.130 Sheet.131 Sheet.132 Sheet.133 Sheet.134 Sheet.135 Sheet.136 Sheet.137 Sheet.138 Sheet.139 Sheet.140 8pt. Arial Text.89 FPGA #1 FPGA #1 8pt. Arial Text.515 Debug Core 1 Debug Core 1 Sheet.143 8pt. Arial Text.96 …… …… 8pt. Arial Text.97 Debug Core n Debug Core n Sheet.146 Sheet.67 X17964-040517 X17964-040517