The following table shows the revision history for this document.
| Section | Revision Summary |
|---|---|
| 04/26/2022 Version 2022.1 | |
| Xilinx Virtual Cable (XVC) | Updated the content. |
| Vivado Debug Bridge IP and Xilinx Virtual Cable (XVC) Flow | Updated From AXI to BSCAN. |
| Xilinx Virtual Cable (XVC) Flow for Versal Devices | Updated the content. |
| Device Configuration Bitstream or PDI Settings | Updated Artix, Virtex, and Kintex UltraScale+ Bitstream Settings, UltraScale Bitstream Settings |
| Configuration Memory Support | Updated all the tables. |