Vivado Design Suite User Guide: Programming and Debugging (UG908) - 2022.1 English - Documents Vivado® tools for programming and debugging a Xilinx® FPGA design. Programming the FPGA includes generating a bitstream file from the implemented design and downloading the file to the target device. Also describes how to debug a design including RTL simulation and in-system debugging. - UG908
Document ID
UG908
Release Date
2022-04-26
Version
2022.1 English
Introduction
Navigating Content by Design Process
Getting Started
Debug Terminology
ILA
VIO
IBERT
JTAG-to-AXI Master
Debug Hub
AXI4 Debug Hub
System ILA
Debug Bridge
In-System IBERT
IBERT GTR
Vivado Lab Edition
Installation
Launching Vivado Lab Edition on Windows
Launching the Vivado Lab Edition from the Command Line on Windows or Linux
Using the Vivado Lab Edition
Starting with a Project
Opening the Hardware Manager
Reviewing Documentation and Videos
Vivado Lab Edition Project
Create a New Project
Creating Projects Using Tcl Commands
Opening the Project
Opening Projects Using Tcl Commands
Using an Existing Device Image and Debug Probes Files in Vivado Lab Edition
Using an Existing .lpr Project from Vivado Design Suite Edition
Programming Features
Debug Features
Generating the Bitstream or Device Image
Changing the Bitstream File Format Settings
Changing the Device Image (.pdi) File Format Settings
Changing Device Configuration Bitstream Settings
Programming the Device
Opening the Hardware Manager
Opening Hardware Target Connections
Connecting to a Hardware Target Using hw_server
Opening a New Hardware Target
Troubleshooting a Hardware Target
Opening a Recent Hardware Target
Opening a Hardware Target Using Tcl Commands
Associating a Programming File with the Hardware Device
Programming the Hardware Device
Incorrect Bitstream Assignment Message
Attempting to Program Configuration Memory Attached to an FPGA Device
Closing the Hardware Target
Closing a Connection to the Hardware Server
Reconnecting to a Target Device with a Lower JTAG Clock Frequency
Connecting to a Server with More Than 32 Devices in a JTAG Chain
Usage
Init Option
Changing the Default SmartLynq Ports
Remote Debugging in Vivado
Using Vivado Hardware Server to Debug Over Ethernet
Xilinx Virtual Cable (XVC)
Vivado Debug Bridge IP and Xilinx Virtual Cable (XVC) Flow
Debug Bridge in XVC Modes
Using Debug Bridge IP in Dynamic Function eXchange Designs
JTAG Fallback Support
MicroBlaze Debug Module (MDM) Support
Multiple Debug Trees
From AXI to BSCAN
From PCIe to BSCAN
From JTAG to BSCAN
From PCIe to JTAG
From AXI to JTAG
Xilinx Virtual Cable (XVC) Flow for Versal Devices
XVC Server Implementation
XVC Protocol
User XVC 1.0 Commands
Initializing Vivado IDE hw_server
Programming Configuration Memory Devices
Changing Device Image Properties
Creating a Configuration Memory File (for FPGA Devices)
Creating a Configuration Memory File for SPI Dual Quad (x8) Devices (for FPGA Devices)
Example write_cfgmem Usage
Creating an Initialization PDI (for Versal Devices)
Connect to the Hardware Target in Vivado
Adding a Configuration Memory Device
Programming a Configuration Memory Device
Programming a Configuration Memory Device (Versal Devices)
Booting the FPGA Device
Configuration Failures in Master Mode
Advanced Programming Features
Readback and Verify
Bitstream Verify and Readback for FPGAs and MPSoCs
Configuration and Boot Memory Verify and Readback for FPGAs or MPSoCs
Generating Encrypted and Authenticated Files for 7 Series Devices
Generating Encrypted and Authenticated Files for UltraScale and UltraScale+
Programming the AES Key for 7 Series Devices
Clearing the AES Key for 7 Series Devices
Programming the AES Key for UltraScale and UltraScale+ Devices
Clearing the AES Key for UltraScale and UltraScale+ Devices
eFUSE Register Access and Programming
Cable Support for eFUSE Programming
eFUSE Register Access and Programming for 7 Series Devices
FUSE_DNA: Unique Device DNA
Programming the eFUSE Registers
Forcing eFUSE Programming
eFUSE Register Access and Programming for UltraScale and UltraScale+ Devices
FUSE_DNA: Unique Device DNA
Programming the eFUSE Registers
Disabling Control Registers Setup
Disabling the JTAG Interface
Forcing eFUSE Programming
eFUSE NKZ File
eFUSE Export NKZ File
System Monitor
System Monitor for Versal Devices
Serial Vector Format (SVF) File Programming
Creating an SVF Target
Using Vivado IDE
Using the Command Line
Adding Devices to an SVF Target
Using Vivado IDE
Using the Command Line
Adding Configuration Memory Parts to Xilinx Devices
Using Vivado IDE
Using Command Line
Operations on the SVF Chain
Writing SVF Files
Using the Vivado IDE
Using the Command Line
Executing SVF Files
Debugging the Design
RTL-Level Design Simulation
Post-Implemented Design Simulation
In-System Logic Design Debugging
In-System Serial I/O Design Debugging
In-System Logic Design Debugging Flows
Probing the Design for In-System Debugging
Versal In-System Debugging
Adding a Control, Interface, and Processing System (CIPS)
AXI4 Debug Hub
AXI4-Stream ILA
AXI4 Debug Hub Connectivity
Manually Connecting Versal Debug Cores
Using the Netlist Insertion Debug Probing Flow
Marking HDL Signals for Debug
Icons and ILA Core
Vivado Synthesis mark_debug Syntax Examples
Synplify mark_debug Syntax Examples
Precision mark_debug Syntax Examples
Synthesizing the Design
Marking Nets for Debug in the Synthesized Design
Using the Set Up Debug Wizard to Insert Debug Cores
Using the Debug Window to Add and Customize Debug Cores
Creating and Removing Debug Cores
Adding, Removing, and Customizing Debug Core Ports
Connecting and Disconnecting Nets to Debug Cores
Modifying Properties on the Debug Cores
Probe as Data or Trigger or Both
Configuring the Number of Comparators Used
Using XDC Commands to Insert Debug Cores
Saving Constraints After Running Debug XDC Commands
Implementing the Design
Debug Core Insertion in Non-Project Mode
HDL Instantiation Debug Probing Flow Overview
Using the HDL Instantiation Debug Probing Flow
Customizing and Generating the Debug Cores
Configuring the Number of Comparators Used
Probe as Data or Trigger
ILA Cross Trigger
Instantiating the Debug Cores
Synthesizing the Design Containing the Debug Cores
Viewing the Debug Cores in the Synthesized Design
Changing the BSCAN User Scan Chain of the Debug Core Hub
Debug Flow in IP Integrator
Debugging Nets and Interfaces in the IP Integrator Block Design
Viewing System ILA Debug Cores in the Synthesized Design
Implementing the Design Containing the Debug Cores
Implementing the Design
ILA Core and Timing Considerations
Debug Cores Clocking Guidelines
Debug Core Clocks
Vivado Hardware Manager Clocking Related Error Messages
Debug Hub Insertion Guidelines
Adding Vivado Debug Cores to a Dynamic Function eXchange Design
Debugging Logic Designs in Hardware
Using Vivado Logic Analyzer to Debug the Design
Connecting to the Hardware Target and Programming the Device
Vivado Hardware Manager Dashboards
Default Dashboards
Default Dashboard Windows
Window Controls within a Dashboard
Moving Windows
Resizing Windows
Closing Windows
Window Tabs
Customizing Dashboards
Dashboard Options
Creating New Dashboards
ILA Waveform Window in Dashboards
System Monitor Dashboards
Resetting to Default Dashboards
Closing Dashboards
Saving User Dashboard Preferences and Settings
Setting Up the ILA Core to Take a Measurement
Adding Probes
Writing Debug Probes Information
Reading Debug Probes Information
Renaming Debug Probes
Using Multiple Comparators
Using the ILA Default Dashboard
User-Defined Debug Probes
Creating a User-Defined Debug Probe
GUI Flow
Tcl Flow
Deleting a User-Defined Debug Probe
GUI Flow
Tcl Flow
Persistence of User-Defined Debug Probes
Interacting with a User-Defined Probe
Using Basic Trigger Mode
Adding Probes to Basic Trigger Setup Window
Setting Basic Trigger Compare Values
ILA Probe Compare Value Settings
Setting Basic Trigger Condition
Using Advanced Trigger Mode
Specifying the Trigger State Machine Program File
Editing the Trigger State Machine Program
Compiling the Trigger State Machine
Enabling Trigger In and Out Ports
Configuring Capture Mode Settings
Using BASIC Capture Mode
Configuring the Basic Capture Setup Window
Setting the Number of Capture Windows
Setting the Trigger Position in the Capture Window
Setting the Data Depth of the Capture Window
Running the Trigger
Stopping the Trigger
Using Auto Re-Trigger
Viewing Trigger and Capture Status
Partial Buffer Capture
Basic Trigger Mode Trigger and Capture Status
Advanced Trigger Mode Trigger and Capture Status
Writing ILA Probes Information
Reading ILA Probes Information
Viewing Captured Data from the ILA Core in the Waveform Viewer
Using Waveform ILA Trigger and Export Features
Saving and Restoring Captured Data from the ILA Core
Saving Captured ILA Data to a File
Probe Data Radix
Listing data samples associated with a single probe
Restoring Captured ILA Data from a File
Enumeration of Probe Values
Add/Edit Enumerations
Define New Enumerations Using the Hardware Manager
Editing Enumeration Associated with a Debug Probe in the Trigger Setup Window
Add Enumerations Using Tcl Commands
Delete Enumerations Using Tcl Commands
Access Enumeration
Using Enumerations in Trigger Setup Window
Using Enumerations in Capture Setup Window
Advanced Trigger
Using Enumerations in the Waveform Window
Debugging AXI Interfaces in the Hardware Manager
Waveform and AXI Interfaces
AXI Transactions in the Waveform Viewer
AXI Interface Events
AXI Transactions
AXI Channel Events
Read Address (AR) Channel Events
Read Address Channel Signal Group
Read Data Channel Events
Read Data Channel Signal Group
Write Address Channel Events
Write Address Channel Signal Group
Write Data Channel Events
Write Data Channel Signal Group
Write Response Channel Events
Write Response Channel Signal Group
Triggering on AXI Address Command and Data Beats
Setting Up the VIO Core to Take a Measurement
Viewing the VIO Core Status
Viewing VIO Cores in the Debug Probes Window
Using the VIO Dashboard
Interacting with VIO Core Input Probes
Reading VIO Inputs Using the VIO Cores View
Setting the VIO Input Display Type and Radix
Observing and Controlling VIO Input Activity
Interacting with VIO Core Output Probes
Writing VIO Outputs Using the VIO Cores View
Setting the VIO Output Display Type and Radix
Resetting the VIO Core Output Values
Synchronizing the VIO Core Output Values to the Vivado IDE
Hardware System Communication Using the JTAG-to-AXI Master Debug Core
Interacting with the JTAG-to-AXI Master Debug Core in Hardware
Resetting the JTAG-to-AXI Master Debug Core
Creating and Running a Read Transaction
Creating and Running a Write Transaction
Using Vivado Logic Analyzer in a Lab Environment
Connecting to a Remote hw_server Running on a Lab Machine
Description of Hardware Manager Tcl Objects and Commands
Description of hw_server Tcl Commands
Description of hw_target Tcl Commands
Description of hw_device Tcl Commands
Description of hw_ila Tcl Commands
Description of hw_ila_data Tcl Commands
Description of hw_probe Tcl Commands
Description of hw_vio Tcl Commands
Description of hw_axi and hw_axi_txn Tcl Commands
Description of hw_sysmon Tcl Commands
Using Tcl Commands to Interact with a JTAG-to-AXI Master Core
Example Tcl Command Script
Using Tcl Commands to Take an ILA Measurement
Example Tcl Command Script
Trigger At Startup
Memory Calibration Debug
Memory Calibration Debug GUI Usage
Memory Calibration Debug Tcl Usage
DDRMC Calibration Debug GUI Usage
DDRMC Calibration Debug Tcl Usage
Debugging Dynamic Function eXchange (DFX) Designs in Vivado Hardware Manager
High Bandwidth Memory (HBM) Monitor
HBM Monitor GUI Usage
HBM Monitor Tcl Usage
PCI Express Link Debug
Enabling PCI Express Link Debug
PCI Express Link Debug GUI Usage
ChipScoPy API
Viewing ILA Probe Data in the Waveform Viewer
ILA Data and Waveform Relationship
Waveform Viewer Layout
Waveform Viewer Operation
Removing Probes from the Waveform
Adding Probes to the Waveform
Using Waveform ILA Trigger and Export Features
Using the Zoom Features
Waveform Settings
Customizing the Configuration
Cursors
Markers
Trigger Markers
Dividers
Using Groups
Using Virtual Buses
Renaming Objects
Radixes
Using the Floating Ruler
Bus Bit Order
Bus Radixes
Viewing Analog Waveforms
Bus Plot Viewer
Creating a Bus Plot
Example of Bus Plot Creation
Zoom Gestures
Debugging Designs Post Implementation
Using Vivado ECO Flow to Replace Existing Debug Probes
Replacing Debug Probes on a Placed and Routed Design Checkpoint
Vivado ECO TCL Flow to Replace Existing Debug Probes
Incremental Compile with Debug Core (ILA) Modifications
Incremental Compile Flow Designs
Reference Design
Current Design
Using Incremental Compile
Using Incremental Compile in Non-Project Mode
Using Incremental Compile in Project Mode
Examining the Similarity Between the Reference Design and the Current Design
Serial I/O Hardware Debugging Flows
Serial I/O Hardware Debugging Flows
Generating an IBERT Core using the Vivado IP Catalog
Generating and Implementing the IBERT Example Design
In-System IBERT System Serial I/O Design Debugging Flows
Generating an In-System IBERT Core Using the Vivado IP Catalog
Instantiating the IP and integrating In-System IBERT IP in the User Design
Versal Serial I/O Hardware Debugging Flows
Debugging the Serial I/O Design in Hardware
Using Vivado Serial I/O Analyzer to Debug the Design
Connecting to the Hardware Target and Programming the Device
Creating Links and Link Groups
Viewing and Changing Links Settings Using the Links Window
Creating and Running Link Scans
Creating and Running Link Sweeps
Displaying and Navigating the Scan Plots
Writing the Scan Results to a File
Properties Window
Description of Serial I/O Analyzer Tcl Objects and Commands
Description of Tcl Commands to Access Hardware
Description of hw_sio_link Tcl Commands
Description of hw_sio_linkgroup Tcl Commands
Description of hw_sio_scan Tcl Commands
Description of Tcl Commands to Get Objects
Using Tcl Commands to Take an IBERT Measurement
Example Tcl Command Script
Viewing Slicer Eye, Histogram, and Signal-to-Noise Ratio (GTM Transceivers Only)
Device Configuration Bitstream or PDI Settings
7 Series Bitstream Settings
Artix, Virtex, and Kintex UltraScale+ Bitstream Settings
UltraScale Bitstream Settings
Zynq UltraScale+ MPSoC Bitstream Settings
Zynq-7000 Bitstream Settings
Versal ACAP Programmable Device Image (PDI) Settings
Trigger State Machine Language Description
States
Goto Action
Conditional Branching
Counters
Flags
Conditional Statements
Debug Probe Conditions
Counter Conditions
Combined Debug Probe and Counter Conditions
Trigger State Machine Language Grammar
Low Level SVF JTAG Commands
Header Data Register (HDR), Header Instruction Register (HIR)
Syntax
Purpose
General Information
TDR, TIR (Trailer Data Register, Trailer Instruction Register)
Syntax
Purpose
General Information
Example
scan_ir_hw
Syntax
General Information
Example
scan_dr_hw
Syntax
General Information
Example
Multi Chain SVF Operation
Multi Chain SVF Operation with Configuration Memory Attached to First Device
Multi Chain SVF Operation with Configuration Memory Attached to Second Device in Chain
Multi Chain SVF Operation with Configuration Memory Attached to Third Device in Chain
JTAG Cables and Devices Supported by hw_server
Programming FTDI Devices for Vivado Hardware Manager Support
Configuration Memory Support
Artix-7 Configuration Memory Devices
Kintex-7 Configuration Memory Devices
Spartan-7 Configuration Memory Devices
Virtex-7 Configuration Memory Devices
Artix UltraScale+ Configuration Memory Devices
Kintex UltraScale Configuration Memory Devices
Kintex UltraScale+ Configuration Memory Devices
Virtex UltraScale Configuration Memory Devices
Virtex UltraScale+ Configuration Memory Devices
Zynq-7000 Configuration Memory Devices
Zynq UltraScale+ MPSoC Configuration Memory Devices
Zynq UltraScale+ RFSoC Configuration Memory Devices
Versal Configuration Memory Devices
Command Line Options for hw_server
Standard hw_server Options
Advanced Options
Additional Resources and Legal Notices
Xilinx Resources
Solution Centers
Documentation Navigator and Design Hubs
References
Training Courses
Revision History
Please Read: Important Legal Notices