From JTAG to BSCAN - 2022.1 English

Vivado Design Suite User Guide: Programming and Debugging (UG908)
Document ID
UG908
Release Date
2022-04-26
Version
2022.1 English

This bridge type is intended for designs that use Xilinx Virtual Cable (XVC) to remotely debug an FPGA or SoC device through Ethernet or other interfaces without the need for JTAG cable. In this mode, the Debug Bridge expects to receive XVC commands via JTAG interface driven by user logic. For more information see the Debug Bridge LogiCORE IP Product Guide (PG245).

Figure 1. JTAG to BSCAN Debug Bridge
Page-1 Process.20 Target Board Target Board Sheet.4 Sheet.5 8pt. Arial Text.29 Data Center Data Center 10pt. Arial Text.55 Processor XVC Server ProcessorXVC Server Sheet.10 8pt. Arial Text.69 GPIO/Custom Interface GPIO/CustomInterface Sheet.13 10pt. Arial Text.9 hw_server hw_server Process.15 Vivado_Logo_FINAL.23 Sheet.17 Sheet.18 Sheet.19 Sheet.20 Sheet.21 Sheet.22 Sheet.23 Sheet.24 Sheet.25 Sheet.26 Sheet.28 Process.85 Sheet.30 8pt. Arial Text.86 User Logic User Logic 8pt. Arial Text.88 JTAG JTAG Sheet.33 Process.507 Debug Bridge (From JTAG to BSCAN) Debug Bridge(From JTAG to BSCAN) 8pt. Arial Text.91 BSCAN BSCAN Sheet.36 10pt. Arial Text.99 10pt. Arial Text.100 8pt. Arial Text.101 User Solution User Solution 8pt. Arial Text.102 Vivado Solution Vivado Solution 8pt. Arial Text.104 Target FPGA Target FPGA Process.156 Xilinx_Logo_corp_4C.519 Sheet.49 Sheet.50 Sheet.51 Sheet.52 Sheet.53 Sheet.54 Sheet.55 Sheet.56 Sheet.57 Sheet.58 Sheet.59 Sheet.60 Process.93 Debug Hub Debug Hub 8pt. Arial Text.515 Debug IP 1 (eg ILA, VIO etc) Debug IP 1 (eg ILA, VIO etc) Sheet.66 8pt. Arial Text.96 …… …… 8pt. Arial Text.97 Debug IP n (eg ILA, VIO etc) Debug IP n (eg ILA, VIO etc) Sheet.69 8pt. Arial Text.512 XVC over TCP/IP XVC overTCP/IP Sheet.63 X17963-092816 X17963-092816