From AXI to BSCAN - 2022.1 English

Vivado Design Suite User Guide: Programming and Debugging (UG908)
Document ID
UG908
Release Date
2022-04-26
Version
2022.1 English

This bridge type is intended for designs using Xilinx® Virtual Cable (XVC) to remotely debug an FPGA or SoC device through Ethernet or other interfaces without the need for JTAG cable. In this mode, the Debug Bridge expects to receive Xilinx® Virtual Cable commands via AXI4-Lite interface. Use this mode to debug designs on the FPGA device over the Xilinx® Virtual Cable.

For more information, see the Debug Bridge LogiCORE IP Product Guide (PG245).

Figure 1. AXI to BSCAN Debug Bridge
Page-1 Process.20 Sheet.5 Sheet.6 8pt. Arial Text.29 Data Center Data Center 8pt. Arial Text.69 XVC over TCP/IP XVC over TCP/IP Sheet.9 10pt. Arial Text.9 hw_server hw_server Process.11 Vivado_Logo_FINAL.23 Sheet.13 Sheet.14 Sheet.15 Sheet.16 Sheet.17 Sheet.18 Sheet.19 Sheet.20 Sheet.21 Sheet.22 Process.85 8pt. Arial Text.86 Zynq Processor XVC Server ZynqProcessorXVC Server 8pt. Arial Text.88 AXI AXI Sheet.89 Process.507 Debug Bridge (From AXI to BSCAN) Debug Bridge(From AXI to BSCAN) 8pt. Arial Text.91 BSCAN BSCAN Sheet.92 10pt. Arial Text.99 10pt. Arial Text.100 8pt. Arial Text.101 User Solution User Solution 8pt. Arial Text.102 Vivado Solution Vivado Solution 8pt. Arial Text.104 Target Board/FPGA Target Board/FPGA Xilinx_Logo_corp_4C.519 Sheet.158 Sheet.159 Sheet.160 Sheet.161 Sheet.162 Sheet.163 Sheet.164 Sheet.165 Sheet.166 Sheet.167 Sheet.168 Sheet.169 Process.93 Debug Hub Debug Hub 8pt. Arial Text.515 Debug IP 1 (eg ILA, VIO etc) Debug IP 1 (eg ILA, VIO etc) Sheet.172 8pt. Arial Text.96 …… …… 8pt. Arial Text.97 Debug IP n (eg ILA, VIO etc) Debug IP n (eg ILA, VIO etc) Sheet.175 Sheet.105 X17961-092816 X17961-092816 Sheet.68