To specify a design checkpoint file (DCP) to use as the reference design, and to run incremental place in Non-Project Mode:
- Load the current design.
- Run debug core commands.
- Run
opt_design
.Important: Make sure theopt_design
options and directives match those used in the original reference run as closely as possible. - Run
read_checkpoint -incremental <reference_dcp_file>
. - Run
place_design
. - Run
route_design
.# to load the current design link_design; #Create the debug core create_debug_core u_ila_0 ila #set debug core properties set_property C_DATA_DEPTH 1024 [get_debug_cores u_ila_0] set_property C_TRIGIN_EN false [get_debug_cores u_ila_0] set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0] set_property C_ADV_TRIGGER false [get_debug_cores u_ila_0] set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_0] set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_0] set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0] set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_0] #connect the probe ports in the debug core to the signals being probed in the design set_property port_width 1 [get_debug_ports u_ila_0/clk] connect_debug_port u_ila_0/clk [get_nets [list clk ]] set_property port_width 1 [get_debug_ports u_ila_0/probe0] connect_debug_port u_ila_0/probe0 [get_nets [list A_or_B]] create_debug_port u_ila_0 probe opt_design read_checkpoint -incremental <reference_dcp_file> place_design route_design
Important: You must open the synthesized checkpoint to modify the debug cores in the design. Insertion of debug cores by opening a post-routed checkpoint is not supported.