UNIMACRO Library - 2022.1 English

Vivado Design Suite User Guide: Logic Simulation (UG900)

Document ID

UG900

Release Date

2022-04-21

Version

2022.1 English

The UNIMACRO library is used during functional simulation and contains macro descriptions for selected device primitives.

Important: You must specify the UNIMACRO library anytime you include a device macro listed in the Vivado Design Suite 7 Series FPGA and Zynq-7000 SoC Libraries Guide (UG953).

VHDL UNIMACRO Library

To use these primitives, place the following two lines at the beginning of each file:

library UNIMACRO;
use UNIMACRO.Vcomponents.all;

Verilog UNIMACRO Library

In Verilog, the individual library modules are specified in separate HDL files. This allows the -y library specification switch to search the specified directory for all components and automatically expand the library.

The Verilog UNIMACRO library does not need to be specified in the HDL file prior to using the modules as is required in VHDL. To use the library module, specify the module name using all uppercase letters. You must also compile and map the library; the method you use depends on the simulator you choose.

Important: Verilog module names and file names are uppercase. For example, module BUFG is BUFG.v. Ensure that UNIMACRO primitive instantiations adhere to an uppercase naming convention.